Abstract: A focus monitor structure is placed on a reticle or mask near the production device structures, such as integrated circuits, to monitor the focal conditions of the lithography process as well as other parameters, such as the critical dimension, and proximity effects. The focus monitor structure includes a series of densely packed parallel lines and an isolated line along with a line that is positioned orthogonally to the densely packed lines forming an "L" shaped structure. The focus monitor structure also includes a plurality of rectangular islands that create post structures when patterned in the resist layer. The lines of the focus monitor structure are approximately the critical dimension and the rectangular islands vary in width between .+-.10% of the critical dimension.

Abstract: A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is deposited on the siliconoxynitride hardmask layer and is exposed to light, the photoresist layer is patterned more conformingly to a desired pattern. The present invention may be used to particular advantage for etching contiguous trench lines and via holes in a dual damascene etch process for small dimension integrated circuits.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Abstract: The present invention provides a method of detecting a lens aberration in a semiconductor production process, comprising the steps of:forming a feature on a substrate by a process including a step of exposing a radiation-sensitive material to radiation, wherein said radiation passes through a lens;obtaining data relating to a sidewall angle at a plurality of adjacent locations of said feature by scanning at least one surface of said feature with an atomic force microscope;calculating the sidewall angle at said plurality of adjacent locations of said feature based on the data obtained by the atomic force microscope;comparing the sidewall angle obtained from the calculation step to a design sidewall angle for a lens free of aberration, thereby detecting the lens aberration when the comparison reveals a substantial difference between the calculated side wall angle and the design sidewall angle; andidentifying a lens position of the lens aberration by extrapolating from the locations of said feature having said s

Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the material. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the material. The measuring system provides material temperature related data to a processor which determines the temperature of the respective portions of the material. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the material and provides for the heating thereof.

Abstract: An integrated circuit manufacturing process for substantially eliminating negative electrostatic charge on a wafer surface after resist processing, comprising contacting the wafer with a dilute electrolyte solution having positive ions, restores the fidelity of CD's as measured by low-voltage SEM'S.

Abstract: A method for reducing stress in a TiN layer of a metallization structure, and a silicon wafer portion made by this method. The surface of the dielectric under the TiN is roughened using a water polish with a hard pad, to provide micromounts and valleys on the dielectric surface.

Abstract: A method of hardening photoresist (24) by bombardment with ionized particles (42), such as argon. Ionic bombardment causes formation of a hardened skin (22) on the exposed top (30) and side walls (32) of the photoresist (24). The hardened skin erodes at a reduced rate during etching and is less likely to react with products created during etching, thereby allowing etching of more accurate line widths and gaps.

Abstract: The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

Abstract: Gaseous sulfur trioxide is used to remove various organic coatings, polymerized photoresist, and especially implant and deep-UV hardened photoresist layers, during the manufacture of semiconductor or ceramic devices.