Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices.

Abstract: An IC is provided. The IC includes a power grid including Mx layer interconnects extending in a first direction on an Mx layer and Mx+1 layer interconnects extending in a second direction orthogonal to the first direction on an Mx+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the Mx layer and the Mx+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.

Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.

Abstract: Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.