Abstract: A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

Abstract: Systems with object detection capabilities may include a radio detection and ranging (RADAR) system. The RADAR system or other portions of the systems may include analog-to-digital converter circuitry. The analog-to-digital converter circuitry may be implemented as pipeline analog-to-digital converter circuitry having multiple stages. Each stage may include multiplying digital-to-analog converter circuitry having a sampling network and amplifier circuitry. The amplifier circuitry may be implemented as a two-stage amplifier. One or more transistors in the two-stage amplifier may receive adaptive control signals that counteract bias current changes across the one or more transistors due to supply voltage changes.

Abstract: A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

Abstract: Systems with object detection capabilities may include a radio detection and ranging (RADAR) system. The RADAR system or other portions of the systems may include analog-to-digital converter circuitry. The analog-to-digital converter circuitry may be implemented as pipeline analog-to-digital converter circuitry having multiple stages. Each stage may include multiplying digital-to-analog converter circuitry having a sampling network and amplifier circuitry. The amplifier circuitry may be shared be shared between multiple stages. The amplifier circuitry may include cascodes for switching between different input pairs from corresponding sampling networks in corresponding stages. The amplifier circuitry may generate amplifier outputs for a first sampling network while the other sampling network performs sampling operations. This may minimize non-amplification time for the amplifier circuitry reduce power consumption in the converter circuitry.

Abstract: An image sensor may include active pixel rows that are used to generate image signals in various modes of operation. The active pixel rows may receive control signals that have corresponding sets of transitions. These sets of transitions may occur during readout operations for some active pixel rows but not during readout operations for other active pixel rows, especially in the case where frames of multiple types are generated by the same pixel array in an interweaved manner. This can lead to different readout environments for readout operations corresponding to different active pixel rows due to control signal coupling effects. To mitigate these adverse effects, an image sensor may include dummy pixel rows that continuously pulse the sets of transitions during the readout operation of any active pixel row to ensure that the readout operations for all active pixel rows have the same readout environments.

Abstract: An image sensor may include image pixels arranged in rows and columns. The image pixels may include respective overflow transistors and overflow capacitors and be configured to generate overflow charge during image acquisition. The overflow charge may be generated in a rolling manner on a row-to-row basis by repeatedly activating the overflow transistors and transfer transistors. Row control circuitry may be configured to provide a final synchronous overflow and transfer transistor activation across all of the pixel rows to provide a uniform overflow charge integration time period across all of the pixel rows. Row control circuitry may include a control signal generation circuit configured to generate control signals having full assertions in a first mode and partial assertions for the final synchronous overflow and transfer transistor activation in a second mode.

Abstract: An image sensor may include image pixels arranged in rows and columns. The image pixels may include an anti-blooming transistor controlled by a first control signal and a transfer transistor controlled by a second control signal. The first and second control signals are generated based on different sets of phases. The different sets of phases are offset from each other. By having a delayed or offset set of phases, the first and second control signals may be asserted independently from each other thereby providing shorter integration time periods during a light flicker mitigation mode of operation. An additional set of phases may be added before readout operations to account for the delay and ensure proper readout operations.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry that provides control signals to the array of imaging pixels. In order to enable the row control circuitry to provide control signals to the array of imaging pixels that have a voltage greater than the power supply voltage, the row control circuitry may include voltage booster circuitry. The voltage booster circuitry may include two amplifiers and may be operable in three different modes. In the first mode, only the second amplifier may be enabled and the output voltage may be between 0V and 2.0V. In the second mode, both the first and second amplifiers may be enabled and the output voltage may be between 2.0V and 2.8V. In the third mode, only the first amplifier may be enabled and the output voltage may be between 2.8V and 4.0V.

Abstract: An image sensor may include active pixel rows that are used to generate image signals in various modes of operation. The active pixel rows may receive control signals that have corresponding sets of transitions. These sets of transitions may occur during readout operations for some active pixel rows but not during readout operations for other active pixel rows, especially in the case where frames of multiple types are generated by the same pixel array in an interweaved manner. This can lead to different readout environments for readout operations corresponding to different active pixel rows due to control signal coupling effects. To mitigate these adverse effects, an image sensor may include dummy pixel rows that continuously pulse the sets of transitions during the readout operation of any active pixel row to ensure that the readout operations for all active pixel rows have the same readout environments.

Abstract: An image sensor may include image pixels arranged in rows and columns. The image pixels may include respective overflow transistors and overflow capacitors and be configured to generate overflow charge during image acquisition. The overflow charge may be generated in a rolling manner on a row-to-row basis by repeatedly activating the overflow transistors and transfer transistors. Row control circuitry may be configured to provide a final synchronous overflow and transfer transistor activation across all of the pixel rows to provide a uniform overflow charge integration time period across all of the pixel rows. Row control circuitry may include a control signal generation circuit configured to generate control signals having full assertions in a first mode and partial assertions for the final synchronous overflow and transfer transistor activation in a second mode.

Abstract: An image sensor may include image pixels arranged in rows and columns. The image pixels may include an anti-blooming transistor controlled by a first control signal and a transfer transistor controlled by a second control signal. The first and second control signals are generated based on different sets of phases. The different sets of phases are offset from each other. By having a delayed or offset set of phases, the first and second control signals may be asserted independently from each other thereby providing shorter integration time periods during a light flicker mitigation mode of operation. An additional set of phases may be added before readout operations to account for the delay and ensure proper readout operations.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry. Each imaging pixel may include a photodiode, a floating diffusion region, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a dual conversion gain transistor coupled to the floating diffusion region, and a storage capacitor coupled to the dual conversion gain transistor. The capacitor may have a plate that receives a modulated control signal and the row control circuitry may be configured to modulate the control signal. To reduce image artifacts, the modulated control signal may be modulated low during the integration time of the pixel and may be modulated high during the high conversion gain readout time of the pixel.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry that provides control signals to the array of imaging pixels. In order to enable the row control circuitry to provide control signals to the array of imaging pixels that have a voltage greater than the power supply voltage, the row control circuitry may include voltage booster circuitry. The voltage booster circuitry may include two amplifiers and may be operable in three different modes. In the first mode, only the second amplifier may be enabled and the output voltage may be between 0V and 2.0V. In the second mode, both the first and second amplifiers may be enabled and the output voltage may be between 2.0V and 2.8V. In the third mode, only the first amplifier may be enabled and the output voltage may be between 2.8V and 4.0V.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry. Each imaging pixel may include a photodiode, a floating diffusion region, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a dual conversion gain transistor coupled to the floating diffusion region, and a storage capacitor coupled to the dual conversion gain transistor. The capacitor may have a plate that receives a modulated control signal and the row control circuitry may be configured to modulate the control signal. To reduce image artifacts, the modulated control signal may be modulated low during the integration time of the pixel and may be modulated high during the high conversion gain readout time of the pixel.