Abstract: A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.

Abstract: A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.

Abstract: A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.