Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.