Abstract: An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

Abstract: The disclosed technology provides a system and a method for adaptive MPEG noise reduction. In particular, the disclosed technology provides a system and a method for reducing blocking artifacts and mosquito noise in an MPEG video signal. An overall MPEG noise detector may be used to determine the presence of noise in one or more frames of a video signal. When a sufficient amount of noise is detected in the one or more frames of the video signal, portions of the video signal that contain noise may be located and filtered to reduce the amount of noise present in the video signal.

Abstract: Disclosed herein are systems and methods for estimating global and local motions between a pair of temporally adjacent frames of an input signal and for applying these motion vectors to produce at least one interpolated, motion-compensated frame between the adjacent frames. In particular, the systems and methods comprise designs for a motion compensated frame rate converter including a global affine motion estimation engine, a global translation motion estimation engine, a segmentation mask generator, an object edge strength map generator and a local motion estimation engine. Combinations of these features are implemented in a motion compensated picture rate converter to accurately and efficiently provide motion estimation and compensation for a sequence of frames.

Abstract: The disclosed technology provides a system and a method for adaptive MPEG noise reduction. In particular, the disclosed technology provides a system and a method for reducing blocking artifacts and mosquito noise in an MPEG video signal. An overall MPEG noise detector may be used to determine the presence of noise in one or more frames of a video signal. When a sufficient amount of noise is detected in the one or more frames of the video signal, portions of the video signal that contain noise may be located and filtered to reduce the amount of noise present in the video signal.

Abstract: A filter for implementing Floyd Steinberg two-dimensional error diffusion algorithms allows high-speed processing of video and images. The filter is shown in direct form with proper bit precision with implementations that permit the filter to operate at high speed. Furthermore, a reduction in the gate count is achieved over the direct form. The results of static timing analysis obtained post synthesis are also summarized.

Abstract: High-frequency noise is generated that approximates the appearance of traditional “film grain” for a digital video signal. By adding a relatively small amount of film grain noise, the video can be made to look more natural and more pleasing to the human viewer. The digital film grain generation can be used to mask unnatural smooth artifacts in digital video such as “blockiness” and “contouring” in the case of compressed video and/or used to provide visual enhancements or special effects to any digital video stream. The digital film grain generator can control grain size and the amount of film grain to be added.

Abstract: A video noise reducer reduces the noise artifacts in a video signal. The video noise reducer is reconfigurable to provide spatial noise reduction and temporal noise reduction in either a parallel or cascade architecture. The video noise reducer is self-calibrating by providing estimation modules that estimate the amount of noise in the video signal and a noise injector that confirms the measurement against a known quantity of noise. The video noise reducer is adaptive to solutions in hardware or a combination of hardware and firmware. The video noise reducer is also optimized for efficient memory usage in interlaced video signal processing applications.

Abstract: High-frequency noise is generated that approximates the appearance of traditional “film grain” for a digital video signal. By adding a relatively small amount of film grain noise, the video can be made to look more natural and more pleasing to the human viewer. The digital film grain generation can be used to mask unnatural smooth artifacts in digital video such as “blockiness” and “contouring” in the case of compressed video and/or used to provide visual enhancements or special effects to any digital video stream. The digital film grain generator can control grain size and the amount of film grain to be added.

Abstract: High-frequency noise is generated that approximates the appearance of traditional “film grain” for a digital video signal. By adding a relatively small amount of film grain noise, the video can be made to look more natural and more pleasing to the human viewer. The digital film grain generation can be used to mask unnatural smooth artifacts in digital video such as “blockiness” and “contouring” in the case of compressed video and/or used to provide visual enhancements or special effects to any digital video stream. The digital film grain generator can control grain size and the amount of film grain to be added.

Abstract: A filter for implementing Floyd Steinberg two-dimensional error diffusion algorithms allows high-speed processing of video and images. The filter is shown in direct form with proper bit precision with implementations that permit the filter to operate at high speed. Furthermore, a reduction in the gate count is achieved over the direct form. The results of static timing analysis obtained post synthesis are also summarized.

Abstract: Disclosed herein are systems and methods for estimating global and local motions between a pair of temporally adjacent frames of an input signal and for applying these motion vectors to produce at least one interpolated, motion-compensated frame between the adjacent frames. In particular, the systems and methods comprise designs for a motion compensated frame rate converter including a global affine motion estimation engine, a global translation motion estimation engine, a segmentation mask generator, an object edge strength map generator and a local motion estimation engine. Combinations of these features are implemented in a motion compensated picture rate converter to accurately and efficiently provide motion estimation and compensation for a sequence of frames.

Abstract: A video noise reducer reduces the noise artifacts in a video signal. The video noise reducer is reconfigurable to provide spatial noise reduction and temporal noise reduction in either a parallel or cascade architecture. The video noise reducer is self-calibrating by providing estimation modules that estimate the amount of noise in the video signal and a noise injector that confirms the measurement against a known quantity of noise. The video noise reducer is adaptive to solutions in hardware or a combination of hardware and firmware. The video noise reducer is also optimized for efficient memory usage in interlaced video signal processing applications.

Abstract: Data loss or system corruption due to a power loss in non-volatile memory may be prevented by tracking block status information in block headers and/or in a mini-array comprised of non-volatile memory cells. The block status may be tracked and managed during block allocate, deallocate, and erase operations in order to allow the memory to remain coherent if a power failure occurs.

Abstract: High-frequency noise is generated that approximates the appearance of traditional “film grain” for a digital video signal. By adding a relatively small amount of film grain noise, the video can be made to look more natural and more pleasing to the human viewer. The digital film grain generation can be used to mask unnatural smooth artifacts in digital video such as “blockiness” and “contouring” in the case of compressed video and/or used to provide visual enhancements or special effects to any digital video stream. The digital film grain generator can control grain size and the amount of film grain to be added.

Abstract: In high-density mode, data may be stored in consecutive byte blocks. In low-density mode, a codeword of memory space may have the capacity to store two bytes of data, but may be used to store only a single byte of data. In a multi-level cell architecture where two or more bits may be stored in a single cell, memory address translation circuitry (or other system component) may translate data to be stored in low-density mode. Memory address translation circuitry may adjust the bit ordering of data to be stored to compensate for the consequences of low-density mode. A single flash memory device may have data stored in one portion in low-density mode and data stored in another portion in high-density mode. Error correcting code (ECC) may be applied in high-density mode and not in low-density mode.

Abstract: A method and device for providing a secret region in a flash erase block to store a key. A block of memory may only be read, programmed, or erased if a key is provided which matches the key stored in the secret region of the block.

Abstract: A bi-cosine filter having a scaling technique to process images for up-scaling that does not lead to loss of the high frequency content of the generated image nor leads to image artifact known as waxing and waning is disclosed. The two tap filter (100) includes an input node (102) coupled to receive the image data. A first multiplier (104) couples to receive a first coefficient (C0) and the image data input. The first multiplier (104) multiplies the image data input by the first coefficient (C0) to provide a first product. The image data input is feed through a delay element (106) to delay the image data by a predetermined time period. Delay element (106) connects to a second multiplier (108) that couples to receive a second coefficient (C1). The second multiplier (108) multiplies the time-delayed image data by the second coefficient (C1) to provide a second product.

Abstract: A bi-cosine filter having a scaling technique to process images for up-scaling that does not lead to loss of the high frequency content of the generated image nor leads to image artifact known as waxing and waning is disclosed. The two tap filter (100) includes an input node (102) coupled to receive the image data. A first multiplier (104) couples to receive a first coefficient (C0) and the image data input. The first multiplier (104) multiplies the image data input by the first coefficient (C0) to provide a first product. The image data input is feed through a delay element (106) to delay the image data by a predetermined time period. Delay element (106) connects to a second multiplier (108) that couples to receive a second coefficient (C1). The second multiplier (108) multiplies the time-delayed image data by the second coefficient (C1) to provide a second product.

Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.