Abstract: The techniques disclosed herein are directed to devices, circuits, systems, and techniques to mitigate the impact of side-channel attacks on a cryptography function in a target system. The Razor flip-flops are inserted into critical paths of the cryptography function of the target system, including at rest blocks such as key vaults and data vaults, and also including registers and/or pipelines used for calculations within the cryptography functions. Errors detected by the Razor flip-flops are processed by error detection logic in the cryptographic function, which continues the calculations until completion. The generated key and data value pairs resulting from detected errors are discarded, silently ignored without disrupting the calculation process. The schemes disclosed herein mitigate the impact of side-channel attacks with a digital logic based implementation, with reduced complexity and reduced cost.

Abstract: Generally discussed herein are devices, systems, and methods for secure cryptographic masking. A method can include generating a first random number, determining a result of the first random number modulo a prime number resulting in a second random number, subtracting the second random number from the prime number resulting in a first subtraction result, adding a private key value to the first subtraction result resulting in a first split, and responsive to determining the private key value is less than the random number, providing the first split and the second random number as splits of the private key.

Abstract: Generally discussed herein are devices, systems, and methods for digital signature generation security. A method can include generating, by a first device, a first random number, in generating a signature for a communication, masking, using the first random number, only a private key, a hash of the communication, or a combination thereof, and providing the signature with the communication to a second device.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Apparatus and methods for booting and using a single CPU socket as a multi-CPU partitioned platform. The single CPU socket includes a plurality of core tiles that a partitioned into a plurality of virtual clusters comprising CPU sub-sockets. Each of the CPU sub-sockets in coupled to an Input-Output (IO) tile having an integrated boot support block and comprising a plurality of IO interfaces including at least one IO interface configured to receive boot signals for booting the sub-sockets and an IO interface to access boot firmware stored in a firmware storage device coupled to the IO interface. The integrated boot support block is configured to facilitate booting of each of the plurality of CPU sub-sockets using a shared set of boot resources coupled to the plurality of IO interfaces.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

Abstract: Examples described herein a firmware update device to execute a second firmware, in place of execution of a first firmware, in response to an instruction that causes the firmware update device to execute the second firmware, wherein the second firmware is copied to a buffer prior to execution of the instruction. In some examples, one or more processors are to execute the instruction that causes the firmware update device to execute the second firmware. In some examples, prior to execution of the instruction, a device root of trust is also to validate the second firmware.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.

Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.

Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

Abstract: Embodiments of processors, methods, and systems for reconfiguring a processor without a system reset are described. In an embodiment, a processor includes configuration storage, shadow configuration storage, trigger storage, and a trigger circuit. The trigger circuit is to cause, based on trigger storage content, shadow configuration storage content to be copied to the configuration storage.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Techniques for controlling alignment of conditions between modular functional blocks in an integrated circuit having a hierarchical network of modular functional blocks. The output of each functional block can be logically determined by its external inputs combined with internal state feedback and internal state and is derived from a pattern of prior external inputs. Alignment of output conditions from independent and interdependent functional blocks within the hierarchical network of functional blocks is induced to provide unique conditions by modifying internal state and timing alignments with internal data and internal controls within one or more of the modular functional blocks. Functional outputs from one or more of the modular functional blocks can be monitored based on the modified internal state and timing alignments. Pattern results can be generated based on the monitoring. Test results based on the pattern results can be stored.