Abstract: A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract: Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.

Abstract: A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.

Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.