Patents by Inventor Bharata B. Rao

Bharata B. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8522251
    Abstract: Task placement is influenced within a multiple processor computer. Tasks are classified as either memory bound or CPU bound by observing certain performance counters over the task execution. During a first pass of task load balance, tasks are balanced across various CPUs to achieve a fairness goal, where tasks are allocated CPU resources in accordance to their established fairness priority value. During a second pass of task load balance, tasks are rebalanced across CPUs to reduce CPU resource contention, such that the rebalance of tasks in the second pass does not violate fairness goals established in the first pass. In one embodiment, the second pass could involve re-balancing memory bound tasks across different cache domains, where CPUs in a cache domain share a same last mile CPU cache such as an L3 cache.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bharata B. Rao, Vaidyanathan Srinivasan, Vaddagiri Srivatsa
  • Publication number: 20120180061
    Abstract: Task placement is influenced within a multiple processor computer. Tasks are classified as either memory bound or CPU bound by observing certain performance counters over the task execution. During a first pass of task load balance, tasks are balanced across various CPUs to achieve a fairness goal, where tasks are allocated CPU resources in accordance to their established fairness priority value. During a second pass of task load balance, tasks are rebalanced across CPUs to reduce CPU resource contention, such that the rebalance of tasks in the second pass does not violate fairness goals established in the first pass. In one embodiment, the second pass could involve re-balancing memory bound tasks across different cache domains, where CPUs in a cache domain share a same last mile CPU cache such as an L3 cache.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Bharata B. Rao, Vaidyanathan Srinivasan, Vaddagiri Srivatsa