Patents by Inventor Bharath Karthik VASAN
Bharath Karthik VASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146268Abstract: Examples of circuits and amplifiers include recirculation circuitry to reduce or cancel error currents produced by target bipolar junction transistors (BJTs). In an example, first recirculation circuitry is coupled to the base of a first signal-conveyance BJT and to one of the collector or the emitter of the first signal-conveyance BJT; second recirculation circuitry is coupled to the base of a second signal-conveyance BJT and to one of the collector or the emitter of the second signal-conveyance BJT; and biasing circuitry is coupled to the first and second recirculation circuitry. The recirculation circuitry may be implemented with BJTs or MOSFETs. Configurations are provided in which error current(s) are recirculated between the base and collector/emitter node of each target BJT.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Inventors: Tyler James Archer, Bharath Karthik Vasan, Jerry L. Doorenbos
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Patent number: 11764740Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.Type: GrantFiled: August 31, 2021Date of Patent: September 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tyler James Archer, Joel Martin Halbert, Bharath Karthik Vasan
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Publication number: 20230275082Abstract: In an example, a device includes a semiconductor substrate having a top surface. The device also includes a P-doped well formed in the semiconductor substrate and extending downwardly from the top surface. The device includes a cathode of a diode formed by an N-doped region in the P-doped well. The device also includes an anode of the diode formed by a P-doped region, the P-doped region spaced away from the N-doped region in the P-doped well. The device includes a deep N-type buried layer (DNBL) formed in the semiconductor substrate, the P-doped well formed between the top surface and the DNBL. The device also includes an N-doped well extending from the top surface to the DNBL.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Inventors: Siva Kumar SUDANI, Jerry L. DOORENBOS, YuGuo WANG, Srinivas Kumar PULIJALA, Bharath Karthik VASAN
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Patent number: 11722104Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.Type: GrantFiled: August 31, 2021Date of Patent: August 8, 2023Assignee: Texas Instruments IncorporatedInventors: Tyler James Archer, Paul Gerard Damitio, Joel Martin Halbert, Bharath Karthik Vasan
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Publication number: 20230060318Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Tyler James Archer, Paul Gerard Damitio, Joel Martin Halbert, Bharath Karthik Vasan
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Publication number: 20230069204Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Tyler James Archer, Joel Martin Halbert, Bharath Karthik Vasan
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Patent number: 10931247Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.Type: GrantFiled: March 19, 2019Date of Patent: February 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vadim Valerievich Ivanov, Bharath Karthik Vasan, Piyush Kaslikar, Srinivas K. Pulijala
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Patent number: 10756685Abstract: A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.Type: GrantFiled: December 15, 2018Date of Patent: August 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bharath Karthik Vasan, Vadim Valerievich Ivanov, Piyush Kaslikar, Srinivas K. Pulijala
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Publication number: 20200106409Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.Type: ApplicationFiled: March 19, 2019Publication date: April 2, 2020Inventors: Vadim Valerievich IVANOV, Bharath Karthik VASAN, Piyush KASLIKAR, Srinivas K. PULIJALA
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Publication number: 20200106400Abstract: A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.Type: ApplicationFiled: December 15, 2018Publication date: April 2, 2020Inventors: Bharath Karthik VASAN, Vadim Valerievich IVANOV, Piyush KASLIKAR, Srinivas K. PULIJALA
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Patent number: 10560064Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.Type: GrantFiled: August 29, 2019Date of Patent: February 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven G. Brantley, Bharath Karthik Vasan, Srinivas K. Pulijala, Martijn Snoeij
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Publication number: 20190386622Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Steven G. BRANTLEY, Bharath Karthik VASAN, Srinivas K. PULIJALA, Martijn SNOEIJ
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Patent number: 10511269Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.Type: GrantFiled: June 1, 2018Date of Patent: December 17, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bharath Karthik Vasan, Srinivas K. Pulijala, Steven G. Brantley
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Publication number: 20190334490Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Steven G. BRANTLEY, Bharath Karthik VASAN, Srinivas K. PULIJALA, Martijn SNOEIJ
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Patent number: 10461706Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.Type: GrantFiled: April 30, 2018Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven G. Brantley, Bharath Karthik Vasan, Srinivas K. Pulijala, Martijn Snoeij
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Publication number: 20190097587Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.Type: ApplicationFiled: June 1, 2018Publication date: March 28, 2019Inventors: Bharath Karthik VASAN, Srinivas K. PULIJALA, Steven G. BRANTLEY
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Patent number: 9954496Abstract: At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.Type: GrantFiled: December 20, 2016Date of Patent: April 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven G. Brantley, Bharath Karthik Vasan, John Lawrence Caldwell
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Publication number: 20170179893Abstract: At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.Type: ApplicationFiled: December 20, 2016Publication date: June 22, 2017Inventors: Steven G. BRANTLEY, Bharath Karthik VASAN, John Lawrence CALDWELL