Patents by Inventor Bharath Krishnan

Bharath Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11003651
    Abstract: RI/ORASE history and current transaction data are stored in partitioned fact tables and aggregation tables based on business calendar. Most of associated indexes are locally partitioned indexes. In a typical RI customer environment, partitioned transaction data takes 85% or more of overall RI database space. The benefits of partitioning include easy management of data, enhanced performance, and assistance with backup and recovery. A partition management system provides the ability to create initial partitions and manage existing partitions in ways that allow the size of the partitioned database to exceed a backup limit size.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: Oracle International Corporation
    Inventors: Jing Ge, Allen John Violette, Bharath Krishnan Narayanan, Stephen Eck
  • Publication number: 20200167330
    Abstract: RI/ORASE history and current transaction data are stored in partitioned fact tables and aggregation tables based on business calendar. Most of associated indexes are locally partitioned indexes. In a typical RI customer environment, partitioned transaction data takes 85% or more of overall RI database space. The benefits of partitioning include easy management of data, enhanced performance, and assistance with backup and recovery. A partition management system provides the ability to create initial partitions and manage existing partitions in ways that allow the size of the partitioned database to exceed a backup limit size.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Jing GE, Allen John VIOLETTE, Bharath Krishnan NARAYANAN, Stephen ECK
  • Patent number: 10102142
    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 16, 2018
    Assignee: Nvidia Corporation
    Inventors: Guillermo J. Rozas, Bharath Krishnan, James Van Zoeren
  • Publication number: 20140181462
    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Bharath Krishnan, James Van Zoeren