Patents by Inventor Bharath Kumar Pulicherla

Bharath Kumar Pulicherla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305409
    Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
  • Patent number: 11075282
    Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Zhi-Qiang Wu, Chung-Cheng Wu, Chih-Han Lin, Gwan-Sin Chang
  • Patent number: 11024721
    Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
  • Patent number: 10871647
    Abstract: An EUV collector mirror for an extreme ultra violet (EUV) radiation source apparatus includes an EUV collector mirror body on which a reflective layer as a reflective surface is disposed, a trajectory correcting device attached to or embedded in the EUV collector mirror body and a trajectory correcting device to adjust the trajectory of metal from the reflective surface of the EUV collector mirror body to an opposite side of the EUV collector mirror body.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An Liu, Gwan-Sin Chang, Bharath Kumar Pulicherla, Li-Jui Chen, Sheng-Kang Yu, Chung-Cheng Wu, Zhiqiang Wu
  • Publication number: 20200111893
    Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Zhi-Qiang WU, Chung-Cheng WU, Chih-Han LIN, Gwan-Sin CHANG
  • Publication number: 20200098890
    Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
  • Publication number: 20200041783
    Abstract: An EUV collector mirror for an extreme ultra violet (EUV) radiation source apparatus includes an EUV collector mirror body on which a reflective layer as a reflective surface is disposed, a trajectory correcting device attached to or embedded in the EUV collector mirror body and a trajectory correcting device to adjust the trajectory of metal from the reflective surface of the EUV collector mirror body to an opposite side of the EUV collector mirror body.
    Type: Application
    Filed: July 19, 2019
    Publication date: February 6, 2020
    Inventors: Kuo-An LIU, Gwan-Sin CHANG, Bharath Kumar Pulicherla, Li-Jui CHEN, Sheng-Kang YU, Chung-Cheng WU, Zhiqiang WU
  • Publication number: 20190386114
    Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Zhi-Qiang WU, Chung-Cheng WU, Chih-Han LIN, Gwan-Sin CHANG
  • Patent number: 10510866
    Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Zhi-Qiang Wu, Chung-Cheng Wu, Chih-Han Lin, Gwan-Sin Chang