Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Abstract: A method of operating an embedded universal serial bus (eUSB) repeater includes holding an eUSB receiver and a USB transmitter in active states and holding a USB receiver and an eUSB transmitter in standby states. The method includes receiving by the eUSB receiver a token packet indicative of transmission of a first downstream packet, and transitioning the USB receiver and the eUSB transmitter from the standby states to the active states responsive to the token packet. The method includes transmitting the token packet by the USB transmitter. The method includes receiving by the eUSB receiver a downstream packet or receiving by the USB receiver an upstream packet within a first timeout period after receiving the token packet, and transmitting the downstream packet by the USB transmitter or transmitting the upstream packet by the eUSB transmitter.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: A system includes an eUSB2 transmitter, wherein the eUSB2 transmitter is configured to provide a data set comprising a data packet, default sync bits, and surplus sync bits. The system also includes an eUSB2 to USB 2.0 repeater coupled to the eUSB2 transmitter, wherein the eUSB2 to USB 2.0 repeater is configured to remove the surplus sync bits and to output the data packet and the default sync bits.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An example system may include a signal source that provides an input signal for generating oscillations and a frequency tuning network for tuning frequency of the oscillations. The frequency tuning network may include one or more input circuits configured for receiving the input signal from the signal source, and a plurality of capacitors. The frequency tuning network may be configured to tune the frequency of the oscillations by adjusting at least one parameter or function applicable to capacitance within the frequency tuning network and/or within other components of the system. The frequency tuning network may be configured to tune the frequency of the oscillations by adjusting amplifying of capacitance. Adjusting amplifying of capacitance in the system may include inhibiting amplifying of at least one capacitor within at least one other component of the system.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

Abstract: Methods and systems are provided for generating balanced oscillations in oscillators. An oscillator comprises a resonator input configured to receive, from an electro-mechanical resonator, a resonator signal; and an oscillator core comprising a first and a second complementary inverters forming a first loop and a second loop with the resonator input, respectively. The inverters are programmable to contribute to the resonator signal a first gain or a second gain to generate balanced oscillations in the oscillator, with the first gain being less than an upper threshold gain required to generate parasitic-mode oscillations when starting balanced oscillations, and the second gain being equal to or greater than a lower threshold, gain required to generate resonator-mode oscillations. Each inverter is configured to regulate gain contributed by the inventor based on regulating amount of power received to control the gain.

Abstract: Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

Abstract: A voltage-controlled oscillator and a method for tuning oscillations. The oscillator comprises a resonator input connected to an oscillator core and a frequency tuning network. The oscillator core and resonator input are isolated from the frequency tuning network by inductors. The method comprises generating oscillations, tuning the frequency of the oscillations by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.