Patents by Inventor Bharath Singareddy

Bharath Singareddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus to prevent a false disconnection in universal serial bus devices
    Patent number: 12626026
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: May 12, 2026
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Srijan Rastogi, Bharath Singareddy
  • Technique for limiting transmission of partial symbols in repeater device
    Patent number: 12591531
    Abstract: A repeater device includes a packet input and a packet output. A first path extends from the packet input to the packet output. The first path includes a transmitter having a transmitter input coupled to the packet input, a transmitter output coupled to the packet output, and a transmitter enable. A second path extends in parallel with the first path and includes a variable delay circuit. The variable delay circuit has an input coupled to the packet input and an output coupled to the transmitter enable of the transmitter.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: March 31, 2026
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srijan Rastogi, Bharath Singareddy, Amal Kumar Kundu, Rudravaram Vaishnavi
  • METHODS AND APPARATUS TO PREVENT A FALSE DISCONNECTION IN UNIVERSAL SERIAL BUS DEVICES
    Publication number: 20250021704
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.
    Type: Application
    Filed: November 29, 2023
    Publication date: January 16, 2025
    Inventors: Win Naing Maung, Srijan Rastogi, Bharath Singareddy
  • TECHNIQUE FOR LIMITING TRANSMISSION OF PARTIAL SYMBOLS IN REPEATER DEVICE
    Publication number: 20240143522
    Abstract: A repeater device includes a packet input and a packet output. A first path extends from the packet input to the packet output. The first path includes a transmitter having a transmitter input coupled to the packet input, a transmitter output coupled to the packet output, and a transmitter enable. A second path extends in parallel with the first path and includes a variable delay circuit. The variable delay circuit has an input coupled to the packet input and an output coupled to the transmitter enable of the transmitter.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Srijan Rastogi, Bharath Singareddy, Amal Kumar Kundu, Rudravaram Vaishnavi