Patents by Inventor Bharathi Yogaraj

Bharathi Yogaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for configuring programmable logic devices for deep learning networks
    Patent number: 11023360
    Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: June 1, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Yongfeng Gu, Girish Venkataramani, Wang Chen, Bharathi Yogaraj, Yuteng Zhou, Vibha Patil, Anusha Vasantala, Purshottam Vishwakarma
  • SYSTEMS AND METHODS FOR CONFIGURING PROGRAMMABLE LOGIC DEVICES FOR DEEP LEARNING NETWORKS
    Publication number: 20200151088
    Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
    Type: Application
    Filed: February 7, 2019
    Publication date: May 14, 2020
    Inventors: Yongfeng Gu, Girish Venkataramani, Wang Chen, Bharathi Yogaraj, Yuteng Zhou, Vibha Patil, Anusha Vasantala, Purshottam Vishwakarma