Patents by Inventor BHASKAR GOPALAN

BHASKAR GOPALAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for reducing metastability in CMOS flip-flops
    Patent number: 9729129
    Abstract: A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 8, 2017
    Inventor: Bhaskar Gopalan
  • SYSTEM AND METHOD FOR REDUCING METASTABILITY IN CMOS FLIP-FLOPS
    Publication number: 20160164502
    Abstract: A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 9, 2016
    Inventor: BHASKAR GOPALAN