Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.

Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

Abstract: A method and system for identification of holographic tracking and identification of features of an object. A holograph is created from scattering off the object, intensity gradients are established for a plurality of pixels in the holograms, the direction of the intensity gradient is determined and those directions analyzed to identify features of the object and enables tracking of the object. Machine learning devices can be trained to estimate particle properties from holographic information.

Abstract: A method and system for identification of holographic tracking and identification of features of an object. A holograph is created from scattering off the object, intensity gradients are established for a plurality of pixels in the holograms, the direction of the intensity gradient is determined and those directions analyzed to identify features of the object and enables tracking of the object. Machine learning devices can be trained to estimate particle properties from holographic information.

Abstract: An in-line holographic microscope is used for measurements of micrometer-scale particles and associated suspending fluid medium containing the particles. The system yields heterodyne scattering patterns that may be interpreted with Lorenz-Mie theory to obtain precise time-resolved information on the refractive index of the suspending medium for determining chemical composition, concentrations and makeup thereof. This approach can perform spatially resolved refractometry with measurements on calibrated refractive index standards and monitor chemical concentration in a microfluidic channel. Using commercially available colloidal spheres as probe particles and a standard video camera for detection yields volumetric refractive index measurements with a resolution of 2×10?3 RIU for each probe particle in each holographic snapshot.

Abstract: An in-line holographic microscope is used for measurements of micrometer-scale particles and associated suspending fluid medium containing the particles. The system yields heterodyne scattering patterns that may be interpreted with Lorenz-Mie theory to obtain precise time-resolved information on the refractive index of the suspending medium for determining chemical composition, concentrations and makeup thereof. This approach can perform spatially resolved refractometry with measurements on calibrated refractive index standards and monitor chemical concentration in a microfluidic channel. Using commercially available colloidal spheres as probe particles and a standard video camera for detection yields volumetric refractive index measurements with a resolution of 2×10?3 RIU for each probe particle in each holographic snapshot.