Abstract: Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.

Abstract: A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results.

Abstract: A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space.

Abstract: Improvements are made to standard run length encoding compression techniques to permit frequently occurring repeated bytes to be dynamically redefined or reset to a default value such as a blank character, repeated multiple byte units or strings to be more efficiently coded and run length encoded enhancements allow compression of data where characters are represented by multiple bytes. The Sequence Control Byte (SCB) is modified to communicate indications to a receiver that the compression mode of 1 to N bytes per character is being changed and to indicate what the change is or that a con, non master repeat character frequently encountered in data is being redefined to be another character or that characters are going to be encoded in multiple bytes.

Abstract: A method of transmitting compressed data using a Ziv-Lempel compression/expansion algorithm, using an adaptive Ziv-Lempel (AZL) dictionary modified to a mature state. The mature state is signaled by a time to freeze signal sent as a switch-over signal from a transmitting location to each receiving location. These signals freeze and synchronize the AZL dictionaries at both locations, and starts a translation of the frozen AZL dictionary to a static SZL dictionary--at least at the transmitting location. The SZL dictionary is then used to compress records being transmitted. An index translation process is generates translation information to allow the receiving locations to decompress SZL indices into original characters. The AZL-to-SZL dictionary translation process re-organizes the frozen AZL to an SZL dictionary. The SZL process is used until either the end of the inputted sequence, or a time to unfreeze signal is generated.

Abstract: Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.