Abstract: A distribution element composed of a crossbar-type switch with four independent ports and direct multicast transfer capability which effects a direct interface to applications with an instruction sets for the distribution element, the sets providing for global memory sharing, synchronization, and lossless flow control.

Abstract: The states of a distributed finite state machine composed of a plurality of devices are coordinated by a sequence of operations to effect a self-timed cycle. Each device is arranged to apply a voltage over one or more leads and measure the current on the corresponding leads. With the methodology, while engendering self-timed cycles, the number of leads interconnecting the devices is also minimized.

Abstract: A methodology for developing scalable systems based on a technique for the composition of objects to form a larger, composite object using Interface Cycles, which are canonical programs, hardware, or abstractions which interlock protection, distribution, and coordination of data and control from the objects. The methodology thus allows the interconnected objects to form the new composite object which is subject to the same principles as the underlying objects and which may then used in any stage of the life cycle of a system. An Interface Cycle transitions through discrete phases only by agreement of all object interfaces connected by the Interface Cycle. Protection and data distribution of composite data collected from all the objects are effected under control of the Interface Cycle.

Abstract: A distribution element composed of a crossbar-type switch with four independent ports and direct multicast transfer capability which effects a direct interface to applications with an instruction sets for the distribution element, the sets providing for global memory sharing, synchronization, and lossless flow control.

Abstract: A procedure for establishing a scalable spanning tree over a network composed of nodes and links in which the resources for each node is independent of the size of the network. The procedure involves the selection of a set of states, a set of messages, state transition rules as well as a completion rule to thereby detect the the setting up of the spanning tree. One established, data may be distributed over the spanning tree so that coordination of data is maintained over all the nodes in the network.

Abstract: Circuitry, and associated methodology in a parallel processing system for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus (60) provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with a global clock (31), state alignment circuit (41, 42, 43) to synchronize the processors with the global clock buffers (140, 240, 340) for storing data received off the bus, and circuitry (130, 230, 330) for selectively enabling the buffer to accept those segments of data having addresses allocated to the given processor. To ensure that processing states are aligned, each state alignment circuit inhibits incrementing of the global clock until each corresponding processor transceives necessary data over the bus.

Abstract: A methodology is disclosed for effecting contention-free communication over a plurality of Collision-type lines interconnecting numerous synchronized stations. In broad terms, each station having a message to transmit executes a prescribed encoding/algorithm. Each station also monitors the states of the lines and depending upon the dynamic states of the lines, the lines are associated with prescribed ones of the lines during each bit interval. At any stage of the detection process, if it is determined that a line broadcasts of unique message, then this line is assigned to the station generating the unique message for the remainder of the frame. The remaining lines are then available for reassignment in subsequent bit intervals. The pattern of bits detected at the end of the frame by each of the lines determines successfully transmitted messages.

Abstract: Methodology and associated circuitry (131,141-143, 151,152,161,162,171-174,181) are disclosed for achieving contention-free broadcasting over one or more buses interconnecting a plurality of synchronized stations. In broad terms for the multiple bus case, each station that intends to utilize the buses prepares candidate message frames equalling the number of buses. The first candidate message of each station (301), after a first perturbation, is propagated over the first bus (311); also, the second candidate message of each station (302), after a second perturbation, is propagated over the second bus (312); this process occurs for all buses. Then, any station detecting a mismatch between its most recently propagated bit on a particular bus and the state of that bus deactivates further propagation of the candidate message on that bus. To arrive at the correct candidate message revealed by each bus, the inverse of the original perturbation must be applied to the revealed message.

Abstract: A digital transmission system includes a plurality of stations sharing a common transmission line. Variable length messages, set off by flags, are exchanged between pairs of stations. While a message is being received, the downstream portion of the transmission line is segmented to permit simultaneous use by another station pair. If a message is received from an upstream station while a message is being transmitted downstream, an abort message flag terminates the transmitted message abruptly to permit flowthrough of the received message. When any station is not in use or out of order, it is bypassed to permit use of the transmission line by the rest of the stations.

Abstract: In order to control the transfer of packets of information among a plurality of stations, e.g., digital computers, the instant communications system, station and protocol contemplate first and second oppositely directed signal paths. At least two stations are coupled to both the first and the second signal paths. A station includes arrangements for reading one signal from the first path and for writing another signal on the first path. The one signal is read from the first path by an arrangement which electrically precedes the arrangement for writing the other signal on the first path. A similar read arrangement is electrically preceding a write arrangement on the second path. If the station has a packet to transmit, it can overwrite a busy control field of the one signal packet on either path. Having read the one signal on the path, a logical interpretation may be made within the station as to whether the path is busy or is not busy.

Abstract: Disclosed is a recursive circuit capable of serving as a signal detector or as a signal generator. The circuit comprises a shift register capable of storing multilevel signals, and a feedback network responsive to an input signal and to the output signals of selected stages of the shift register. In the feedback network, the output signals of the selected stages are each multiplied by prechosen integers, and then added with the input signal to form a sum signal which is applied to the first stage of the shift register. The sum signal is developed by nonmodulo addition, and the multiplying integers are prechosen to cause the characteristic function of the circuit to be a cyclotomic polynomial. Detection of the presence in the input signal of a signal having a chosen frequency is accomplished by the sum signal excluding a predetermined threshold level.

Abstract: Disclosed are signal generators for developing multilevel output signal sequences of a preselected period of repetition. In their general form, the generators comprise a shift register capable of storing multilevel signals, and feedback means. The feedback means multiply the output signal of prescribed shift register stages by selected integers, add the multiplied signals in nonmodulo arithmetic, and apply the added signals to the first stage of the shift register. The multiplying integers within the feedback means are selected to cause the characteristic functions of the signal generator to be a cyclotomic polynomial. For descriptive convenience, the disclosed generator is termed a "cyclotomic circuit." The disclosed cyclotomic circuits are particularly useful in a minimum memory, prescribed-period, signal generator applications. The minimum memory is achieved by separating the prescribed period into power-of-prime factors, and by associating with each factor a cyclotomic circuit.