Abstract: Described herein are a device and method for performing a network analysis. In one aspect, the device includes a reconfigurable neural network circuit to determine an indication of a predicted network characteristic. In one aspect, the reconfigurable neural network circuit includes a control circuit to select a packet attribute or a flow attribute of a raw packet stream from a pipeline, and determine a configuration setting corresponding to the packet attribute or the flow attribute. The configuration setting may indicate a configuration of the reconfigurable neural network circuit to implement a neural network. In one aspect, the reconfigurable neural network circuit includes a storage to provide neural network parameters of the neural network, according to the configuration setting.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a reconfigurable neural network circuit to determine an indication of a predicted network characteristic. In one aspect, the reconfigurable neural network circuit includes a control circuit to select a packet attribute or a flow attribute of a raw packet stream from a pipeline, and determine a configuration setting corresponding to the packet attribute or the flow attribute. The configuration setting may indicate a configuration of the reconfigurable neural network circuit to implement a neural network. In one aspect, the reconfigurable neural network circuit includes a storage to provide neural network parameters of the neural network, according to the configuration setting.

Abstract: In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

Abstract: A system can include circuitry. The circuitry can receive an entry index of a table, perform a cycle walk of a first pipeline stage to change the entry index from a first value to a second value, determine that the second value of the entry index is an illegal value, provide the second value of the entry index to a second pipeline stage, and perform a cycle walk of the second pipeline stage to change the entry index to a legal value.

Abstract: A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

Abstract: A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.

Abstract: In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

Abstract: In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

Abstract: In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a reconfigurable neural network circuit to determine an indication of a predicted network characteristic. In one aspect, the reconfigurable neural network circuit includes a control circuit to select a packet attribute or a flow attribute of a raw packet stream from a pipeline, and determine a configuration setting corresponding to the packet attribute or the flow attribute. The configuration setting may indicate a configuration of the reconfigurable neural network circuit to implement a neural network. In one aspect, the reconfigurable neural network circuit includes a storage to provide neural network parameters of the neural network, according to the configuration setting.