Patents by Inventor Bhavana MURALIKRISHNA

Bhavana MURALIKRISHNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable non-linear filter for digital pre-distortion
    Patent number: 11563409
    Abstract: Some embodiments herein describe a radio frequency communication system that can include a transmitter to output an radio frequency (RF) transmit signal, the transmitter including a digital pre-distortion system (DPD) that pre-distorts the RF transmit signal. The DPD system can include a configurable non-linear filter, such as a Laguerre filter, having multiple rows where at least one row operates with a configurable decimation ratio. The DPD system can further include decimators and a crossbar switch coupled between the decimators.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 24, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Anand Venkitasubramani, Stephen Summerfield, Bhavana Muralikrishna, Praveen Chandrasekaran
  • Image scaling
    Patent number: 11463715
    Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: October 4, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Anand Venkitasubramani, Bhavana Muralikrishna, Shreeja Sugathan, Niall D. O'Connell
  • CONFIGURABLE NON-LINEAR FILTER FOR DIGITAL PRE-DISTORTION
    Publication number: 20220131506
    Abstract: Some embodiments herein describe a radio frequency communication system that can include a transmitter to output an radio frequency (RF) transmit signal, the transmitter including a digital pre-distortion system (DPD) that pre-distorts the RF transmit signal. The DPD system can include a configurable non-linear filter, such as a Laguerre filter, having multiple rows where at least one row operates with a configurable decimation ratio. The DPD system can further include decimators and a crossbar switch coupled between the decimators.
    Type: Application
    Filed: June 22, 2021
    Publication date: April 28, 2022
    Inventors: Anand Venkitasubramani, Stephen Summerfield, Bhavana Muralikrishna, Praveen Chandrasekaran
  • IMAGE SCALING
    Publication number: 20210203966
    Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 1, 2021
    Applicant: Analog Devices International Unlimited Company
    Inventors: Anand VENKITASUBRAMANI, Bhavana MURALIKRISHNA, Shreeja SUGATHAN, Niall D. O'Connell
  • Image scaling
    Patent number: 10972744
    Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: April 6, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Anand Venkitasubramani, Bhavana Muralikrishna, Shreeja Sugathan, Niall D. O'Connell
  • IMAGE SCALING
    Publication number: 20200154120
    Abstract: There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 14, 2020
    Applicant: Analog Devices International Unlimited Company
    Inventors: Anand VENKITASUBRAMANI, Bhavana MURALIKRISHNA, Shreeja SUGATHAN, Niall D. O'Connell