Abstract: Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

Abstract: A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

Abstract: A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

Abstract: A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

Abstract: A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback equalizer (DFE). In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, perhaps a DFE. In that embodiment, the circuit includes an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of an eye relative to which said equalizer is configured for operation without substantially affecting said operation.

Abstract: Testing a transceiver includes providing a sequence of test signals. A serialization clock is generated and jitter is added to the clock in a known and controlled manner. The test signals can then be transmitted using the serialization clock. After the test signals are recovered by the clock and data recovery mechanism, the recovered sequence is compared to the original sequence, to test for jitter tolerance. Preferably, each of these steps is performed on chip. In other aspects, a jitter transfer test and/or a FIFO test can be performed.

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: A method, and associated storage medium containing software and a system, comprises extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

Abstract: A filter comprises a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that, permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.

Abstract: A sense amplifier and associated method comprise a regenerative latch, an input differential pair of transistors coupled to the regenerative latch, and a leakage device coupled to each of the transistors comprising the input differential pair of transistors. The leakage device is adapted to maintain the input differential pair of transistors in an on state during a pre-charge phase. In other embodiments, the sense amplifier includes a clocked buffer coupled to the outputs of the regenerative latch. The clocked buffer provides additional drive current for the sense amplifier and is clocked by a clock signal that controls the regenerative latch. In yet other embodiments, the sense amplifier includes a secondary hold latch coupled to the outputs of the regenerative latch to maintain an output decision for the sense amplifier while other portions of the sense amplifier pre-charge.