Patents by Inventor Bhavesh Bhartia

Bhavesh Bhartia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    Publication number: 20230057852
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 23, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, M. Jared Barclay, Bhavesh Bhartia, Chet E. Carter, John D. Hopkins, Andrew Li, Haoyu Li, Alyssa N. Scarbrough, Grady S. Waldo