Patents by Inventor Bhavesh Govindbhai Patel

Bhavesh Govindbhai Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220342899
    Abstract: Techniques described herein relate to a method for provisioning workflows with data transformation services. The method may include receiving, by a platform controller associated with a first domain, workflow information associated with a portion of a workflow to be deployed in a device ecosystem, where the portion of the workflow includes a first subportion of the workflow; identifying an output intent associated with data of the first subportion of the workflow; making a first determination that the output intent is associated with a data transformation of the data; making a second determination that the first domain is able to perform the data transformation; and establishing data transformation services using resources of the first domain; and initiating performance of the first subportion of the workflow, where executing the first subportion of the workflow includes executing the data transformation services.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Inventors: John S. Harwood, Robert Anthony Lincourt, JR., Bhavesh Govindbhai Patel, William Price Dawkins, William Jeffery White
  • Patent number: 10998072
    Abstract: Systems and methods for configurable voltage regulator (VR) controllers. In some embodiments, an Information Handling System (IHS) may include: a processor; and a voltage regulator (VR) coupled to the processor, the VR configured to: identify, via a VR controller, a number of phases coupled to the voltage regulator in response to detection of a power-on-reset event; and select, via the VR controller, one of a plurality of different configuration files to be applied to the voltage regulator in response to the identification.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 4, 2021
    Assignee: Dell Products, L.P.
    Inventors: Mehran Mirjafari, Bhavesh Govindbhai Patel, John J. Breen, Lei Wang
  • Patent number: 10948958
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine an engagement of a power supply unit with at least one of an information handling system (IHS) and a chassis configured to house multiple information handling systems (IHSs); may provide a power at a first voltage to the at least one of the IHS and the chassis; may determine if the at least one of the IHS and the chassis utilizes a second voltage; if the at least one of the IHS and the chassis utilizes the second voltage, may determine if the power supply unit is configured to provide the power at the second voltage; and if the power supply unit is configured to provide the power at the second voltage, may provide the power at the second voltage to the at least one of the IHS and the chassis.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 16, 2021
    Assignee: Dell Products L.P.
    Inventors: Mark A. Muccini, Bhavesh Govindbhai Patel, Lei Wang, Kevin Mundt
  • Publication number: 20200110452
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine an engagement of a power supply unit with at least one of an information handling system (IHS) and a chassis configured to house multiple information handling systems (IHSs); may provide a power at a first voltage to the at least one of the IHS and the chassis; may determine if the at least one of the IHS and the chassis utilizes a second voltage; if the at least one of the IHS and the chassis utilizes the second voltage, may determine if the power supply unit is configured to provide the power at the second voltage; and if the power supply unit is configured to provide the power at the second voltage, may provide the power at the second voltage to the at least one of the IHS and the chassis.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Mark A. Muccini, Bhavesh Govindbhai Patel, Lei Wang, Kevin Mundt
  • Patent number: 10318461
    Abstract: An information handling system includes first and second compute nodes, each compute node including a central processing unit (CPU), a computational accelerator (CAC). An inter-accelerator transport (IAT) interface of each node connects to an IAT transport to provide an external interconnect, directly coupling first node GPUs with second node GPUs, for inter-node GPU-to-GPU (GtG) data traffic. Inter-node adapters on each node connect to an inter-node transport (INT) to provide an external interconnect coupling the GPUs of one node to the CPU/root of the other node for carrying inter-node non-GtG data traffic. Interconnects carrying non-GtG traffic, including the INT, may be ×16 PCIe 3.0 or later links while interconnects carrying GtG traffic, including the IAT interconnects, may be implemented as greater-than-PCIe (GTP) interconnects where GTP interconnects have a data transfer rate exceeding comparable PCIe data transfer rates, e.g., 16 GB/s per ×16 PCIE 3.0.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 11, 2019
    Assignee: Dell Products L.P.
    Inventor: Bhavesh Govindbhai Patel
  • Publication number: 20190042512
    Abstract: An information handling system includes first and second compute nodes, each compute node including a central processing unit (CPU), a computational accelerator (CAC). An inter-accelerator transport (IAT) interface of each node connects to an IAT transport to provide an external interconnect, directly coupling first node GPUs with second node GPUs, for inter-node GPU-to-GPU (GtG) data traffic. Inter-node adapters on each node connect to an inter-node transport (INT) to provide an external interconnect coupling the GPUs of one node to the CPU/root of the other node for carrying inter-node non-GtG data traffic. Interconnects carrying non-GtG traffic, including the INT, may be ×16 PCIe 3.0 or later links while interconnects carrying GtG traffic, including the IAT interconnects, may be implemented as greater-than-PCIe (GTP) interconnects where GTP interconnects have a data transfer rate exceeding comparable PCIe data transfer rates, e.g., 16 GB/s per ×16 PCIE 3.0.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 7, 2019
    Applicant: Dell Products L.P.
    Inventor: Bhavesh Govindbhai PATEL
  • Publication number: 20180335822
    Abstract: Systems and methods for configurable voltage regulator (VR) controllers. In some embodiments, an Information Handling System (IHS) may include: a processor; and a voltage regulator (VR) coupled to the processor, the VR configured to: identify, via a VR controller, a number of phases coupled to the voltage regulator in response to detection of a power-on-reset event; and select, via the VR controller, one of a plurality of different configuration files to be applied to the voltage regulator in response to the identification.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Applicant: Dell Products, L.P.
    Inventors: Mehran Mirjafari, Bhavesh Govindbhai Patel, John J. Breen, Lei Wang
  • Patent number: 9910103
    Abstract: A power supply unit (PSU) performs a PSU fault diagnosis using a PSU fault detection module. The PSU fault detection module detects a diagnostic trigger event and initiates a series of checks of selected sub-systems. The PSU fault detection module determines whether the trigger event occurred while the PSU was connected within an information handling system (IHS) or physically removed from the IHS. If the trigger event occurred while the PSU was connected within an information handling system (IHS), the PSU fault detection module electrically isolates the PSU from the IHS using an ORing device, which blocks current flowing into the PSU. The PSU fault detection module determines whether a short circuit exists within the electrically isolated PSU. If a short circuit is identified, the PSU fault detection module determines that the PSU is not functioning properly and provides a notification of a malfunction of the PSU.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 6, 2018
    Assignee: Dell Products, L.P.
    Inventors: Mehran Mirjafari, Mark Muccini, Scott Michael Ramsey, Wei Chen, Bhavesh Govindbhai Patel
  • Patent number: 9772652
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, an access controller, a real-time clock, and a basic input/output system. The access controller may be communicatively coupled to the processor and configured to execute a client for retrieving real time via a network communicatively coupled to the access controller. The real-time clock may be communicatively coupled to the access controller. The basic input/output system may be embodied in one or more instructions readable and executable by the processor and configured to, during a power-on/self-test of the basic input/output system, read real time from the access controller and write the real time to the real-time clock.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 26, 2017
    Assignee: DELL PRODUCTS L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Mukund P. Khatri
  • Publication number: 20170153294
    Abstract: A power supply unit (PSU) performs a PSU fault diagnosis using a PSU fault detection module. The PSU fault detection module detects a diagnostic trigger event and initiates a series of checks of selected sub-systems. The PSU fault detection module determines whether the trigger event occurred while the PSU was connected within an information handling system (IHS) or physically removed from the IHS. If the trigger event occurred while the PSU was connected within an information handling system (IHS), the PSU fault detection module electrically isolates the PSU from the IHS using an ORing device, which blocks current flowing into the PSU. The PSU fault detection module determines whether a short circuit exists within the electrically isolated PSU. If a short circuit is identified, the PSU fault detection module determines that the PSU is not functioning properly and provides a notification of a malfunction of the PSU.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Applicant: DELL PRODUCTS, L.P.
    Inventors: MEHRAN MIRJAFARI, MARK MUCCINI, SCOTT MICHAEL RAMSEY, WEI CHEN, BHAVESH GOVINDBHAI PATEL
  • Patent number: 9634777
    Abstract: In accordance with embodiments of the present disclosure, a method for characterizing electrical characteristics of a communication channel between a transmitter of a first information handling resource and a receiver of a second information handling resource may include receiving a test signal at the receiver from the transmitter during an in-situ characterization mode of the second information handling resource, converting the test signal into a discrete-time digital signal representing the test signal, generating a discrete-time finite difference function comprising a first derivative of the discrete-time digital signal, transforming the discrete-time finite difference function into a frequency-domain transform of the discrete-time finite difference function.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 25, 2017
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury
  • Patent number: 9537618
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a first information handling resource communicatively coupled to the processor, and a second information handling resource communicatively coupled to the processor and the first information handling resource. The first information handling resource and the second information handling resource may be configured to, in concert determine an optimum delay between opposite polarity signals for differential signals communicated from the first information handling resource to the second information handling resource via a path comprising a differential pair and transmit data from the first information handling resource to the second information handling resource via the path by inserting a delay into one of the opposite polarity signals equal to the optimum delay.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 3, 2017
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury
  • Publication number: 20160254872
    Abstract: In accordance with embodiments of the present disclosure, a method for characterizing electrical characteristics of a communication channel between a transmitter of a first information handling resource and a receiver of a second information handling resource may include receiving a test signal at the receiver from the transmitter during an in-situ characterization mode of the second information handling resource, converting the test signal into a discrete-time digital signal representing the test signal, generating a discrete-time finite difference function comprising a first derivative of the discrete-time digital signal, transforming the discrete-time finite difference function into a frequency-domain transform of the discrete-time finite difference function.
    Type: Application
    Filed: May 10, 2016
    Publication date: September 1, 2016
    Applicant: Dell Products L.P.
    Inventors: Timoth M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury
  • Publication number: 20160248852
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, an access controller, a real-time clock, and a basic input/output system. The access controller may be communicatively coupled to the processor and configured to execute a client for retrieving real time via a network communicatively coupled to the access controller. The real-time clock may be communicatively coupled to the access controller. The basic input/output system may be embodied in one or more instructions readable and executable by the processor and configured to, during a power-on/self-test of the basic input/output system, read real time from the access controller and write the real time to the real-time clock.
    Type: Application
    Filed: February 23, 2015
    Publication date: August 25, 2016
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Mukund P. Khatri
  • Patent number: 9363026
    Abstract: In accordance with embodiments of the present disclosure, a method for characterizing electrical characteristics of a communication channel between a transmitter of a first information handling resource and a receiver of a second information handling resource may include receiving a test signal at the receiver from the transmitter during an in-situ characterization mode of the second information handling resource, converting the test signal into a discrete-time digital signal representing the test signal, generating a discrete-time finite difference function comprising a first derivative of the discrete-time digital signal, transforming the discrete-time finite difference function into a frequency-domain transform of the discrete-time finite difference function.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: June 7, 2016
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury
  • Publication number: 20150103873
    Abstract: In accordance with embodiments of the present disclosure, a method for characterizing electrical characteristics of a communication channel between a transmitter of a first information handling resource and a receiver of a second information handling resource may include receiving a test signal at the receiver from the transmitter during an in-situ characterization mode of the second information handling resource, converting the test signal into a discrete-time digital signal representing the test signal, generating a discrete-time finite difference function comprising a first derivative of the discrete-time digital signal, transforming the discrete-time finite difference function into a frequency-domain transform of the discrete-time finite difference function.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Dell Products L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury
  • Publication number: 20140173367
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a first information handling resource communicatively coupled to the processor, and a second information handling resource communicatively coupled to the processor and the first information handling resource. The first information handling resource and the second information handling resource may be configured to, in concert determine an optimum delay between opposite polarity signals for differential signals communicated from the first information handling resource to the second information handling resource via a path comprising a differential pair and transmit data from the first information handling resource to the second information handling resource via the path by inserting a delay into one of the opposite polarity signals equal to the optimum delay.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: DELL PRODUCTS L.P.
    Inventors: Timothy M. Lambert, Bhavesh Govindbhai Patel, Bhyrav M. Mutnury