Abstract: A hybrid photonic circuit with one or more nonlinear photonic elements. The photonic circuit includes one or more photonic logic gate and one or more nonlinear photonic elements coupled to the one or more photonic logic gate. The one or more photonic logic gates receives one or more photonic input signals and generate one or more photonic intermediate output signals based at least in part on the one or more photonic input signals. The one or more nonlinear photonic elements receive the one or more photonic intermediate output signals and generate one or more photonic output signals through application of a nonlinear transfer function of the one or more nonlinear photonic elements to one or more amplitudes of the one or more photonic intermediate output signals.

Abstract: A photonic circuit configured to operate as a universal photonic gate. The photonic circuit includes at least a first photonic gate and a first nonlinear photonic circuit coupled to the first photonic gate. The first photonic gate receives one or more photonic input signals and generates, based at least in part on the one or more photonic input signals, one or more first photonic intermediate output signals. The first nonlinear photonic circuit receives the one or more first photonic intermediate output signals and generates one or more first photonic output signals by applying a first nonlinear transfer function of the first nonlinear photonic circuit to the one or more first photonic intermediate output signals. A logical function of the photonic circuit depends on phase shifts applied by phase shifters of the first photonic gate and an amplitude value of a bias signal input into the first photonic gate.

Abstract: A photonic processor with multiple layers of feedback. At least one of a first set of photonic adders in the photonic processor includes a feedback path feeding a first feedback signal from a carry output to an input of the at least one first photonic adder. The at least one first photonic adder generates a photonic sum based in part on the first feedback signal. At least one of a second set of photonic adders in the photonic processor includes a feedback path feeding a second feedback signal from a carry output to an input of the least one second photonic adder. The at least one second photonic adder generates an updated version of a photonic input signal based in part on the second feedback signal and the photonic sum. A feedback interface feeds the updated version of the photonic input signal back to an input of the photonic processor.

Abstract: A photonic circuit with at least one nonlinear amplitude thresholder for correcting errors produced by linear photonic logic. One or more photonic input gates of the photonic circuit receive one or more input signals and generate one or more photonic signals based on the one or more photonic input signals. A first set of one or more photonic gates of the photonic circuit generates one or more intermediate photonic signals based on the one or more photonic signals. The at least one nonlinear amplitude thresholder generates at least one photonic thresholding signal based on the one or more intermediate photonic signals, the at least one nonlinear amplitude thresholder operating in a first operating regime, second operating regime, and/or third operating regime. A second set of one or more photonic gates of the photonic circuit generates one or more photonic output signals based on the at least one photonic thresholding signal.

Abstract: Embodiments of the present disclosure are directed to a photonic implementation of a processor for keys update and hash generation for digital currency (e.g., bitcoin) transactions. The processor includes a first photonic circuit and a second photonic circuit coupled to the first photonic circuit via a set of optical connections. The first photonic circuit is configured to generate a plurality of new messages based at least in part on a plurality of input messages. During a plurality of operational cycles, the second photonic circuit is configured to receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and update a plurality of keys based at least in part on the received plurality of new messages. The second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles.

Abstract: A photonic circuit with a semiconductor optical amplifier-based amplitude thresholder for correcting bit errors produced by a passive photonic logic. In addition to the amplitude thresholder, the photonic circuit further includes a plurality of photonic inputs receiving photonic input signals, a first cascaded series of photonic components coupled to the photonic inputs, and a second cascaded series of photonic components coupled to the amplitude thresholder. The first cascaded series of photonic components generates a plurality of intermediate photonic output signals based on the photonic input signals. The amplitude thresholder generates a saturated photonic signal based on a first of the plurality of intermediate photonic output signals when the amplitude thresholder operates in a single nonlinear region.

Abstract: A photonic circuit with at least one semiconductor optical amplifier-based amplitude thresholder for correcting bit errors. The photonic circuit further includes a first cascaded series of one or more photonic components and a second cascaded series of one or more photonic components that is coupled to the at least one amplitude thresholder. The first cascaded series of one or more photonic components generates one or more intermediate photonic output signals based on one or more received photonic input signals. The at least one amplitude thresholder generates one or more thresholding photonic signals based on a first of the one or more photonic output signals. The second cascaded series of one or more photonic components generates one or more photonic output signals based at least in part on a second of the one or more intermediate photonic output signals and the one or more thresholding photonic signals.

Abstract: Embodiments of the present disclosure are directed to an efficient design of a photonic circuit by an emulator circuit that optimizes coefficients of an S-matrix representation model of the photonic circuit. The emulator circuit comprises a first optimizer circuit, a comparator circuit, and a second optimizer circuit. The first optimizer circuit determines target coefficients of a target S-matrix representation model of the photonic circuit, based on photonic input signals and target photonic output signals of the target S-matrix representation model. The comparator circuit compares the target coefficients with device coefficients of an S-matrix representation model of the photonic circuit. The second optimizer circuit iteratively updates the device coefficients based on the comparison to determine final device coefficients. The photonic circuit is defined in accordance with the determined final device coefficients.

Abstract: Embodiments are directed to designing area and power-efficient photonic super-gates. A first modeling circuit of an emulator circuit generates a physical model for a photonic circuit having a plurality of cascaded photonic gates, based on a set of photonic input signals and a set of one or more photonic output signals that are defined in accordance with a truth table of the photonic circuit. Based on the physical model, a first optimizer circuit of the emulator circuit estimates initial parameters of a target model for the photonic circuit. A second modeling circuit of the emulator circuit generates, based on the initial parameters, a set of parameters of the target model. A second optimizer circuit of the emulator circuit executes a design algorithm on the set of parameters of the target model to instantiate a photonic super-gate that emulates operations of the photonic circuit.

Abstract: Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.

Abstract: A system for photonic computing, preferably including: an input module, computation module, and/or control module, wherein the computation module preferably includes one or more filter banks and/or detectors. A photonic filter bank system, preferably including two waveguides and a plurality of optical filters arranged between the waveguides. A method for photonic computing, preferably including: controlling a computation module; controlling an input module; and/or receiving outputs from the computation module.

Abstract: A system for photonic computing, preferably including: an input module, computation module, and/or control module, wherein the computation module preferably includes one or more filter banks and/or detectors. A photonic filter bank system, preferably including two waveguides and a plurality of optical filters arranged between the waveguides. A method for photonic computing, preferably including: controlling a computation module; controlling an input module; and/or receiving outputs from the computation module.

Abstract: A system for photonic computing, preferably including: an input module, computation module, and/or control module, wherein the computation module preferably includes one or more filter banks and/or detectors. A photonic filter bank system, preferably including two waveguides and a plurality of optical filters arranged between the waveguides. A method for photonic computing, preferably including: controlling a computation module; controlling an input module; and/or receiving outputs from the computation module.

Abstract: A system for photonic computing, preferably including: an input module, computation module, and/or control module, wherein the computation module preferably includes one or more filter banks and/or detectors. A photonic filter bank system, preferably including two waveguides and a plurality of optical filters arranged between the waveguides. A method for photonic computing, preferably including: controlling a computation module; controlling an input module; and/or receiving outputs from the computation module.

Abstract: According to some embodiments, a network architecture is disclosed. The network architecture includes a plurality of processing network nodes. The network architecture further includes at least one broadcasting medium to interconnect the plurality of processing network nodes where the broadcasting medium includes an integrated waveguide. The network architecture also includes a broadcast and weight protocol configured to perform wavelength division multiplexing such that multiple wavelengths coexist in the integrated waveguide available to all nodes of the plurality of processing network nodes.

Abstract: According to some embodiments, a network architecture is disclosed. The network architecture includes a plurality of processing network nodes. The network architecture further includes at least one broadcasting medium to interconnect the plurality of processing network nodes where the broadcasting medium includes an integrated waveguide. The network architecture also includes a broadcast and weight protocol configured to perform wavelength division multiplexing such that multiple wavelengths coexist in the integrated waveguide available to all nodes of the plurality of processing network nodes.