Patents by Inventor Bhavna Agrawal

Bhavna Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8290760
    Abstract: A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Bhavna Agrawal, Peter Feldmann, Ying Liu, Steven G. Walker
  • Patent number: 8239794
    Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bhavna Agrawal, David J. Hathaway, Pravin P. Kamdar, Karl K. Moody, III, Peng Peng, David W. Winston
  • Publication number: 20110077882
    Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: International Business Machines Corporation
    Inventors: Bhavna Agrawal, David J. Hathaway, Pravin P. Kamdar, Karl K. Moody, III, Peng Peng, David W. Winston
  • Publication number: 20090192776
    Abstract: A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 30, 2009
    Inventors: Emrah Acar, Bhavna Agrawal, Peter Feldmann, Ying Liu, Steven G. Walker
  • Patent number: 7519526
    Abstract: A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Bhavna Agrawal, Peter Feldmann, Ying Liu, Steven G. Walker
  • Patent number: 7487480
    Abstract: A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Bhavna Agrawal, David J. Hathaway, Peng Peng
  • Publication number: 20080155484
    Abstract: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 26, 2008
    Inventors: Bhavna Agrawal, Peter Feldmann, Sani R. Nassif, Tomasz J. Nowicki, Grzegorz Michal Swirszcz
  • Patent number: 7350170
    Abstract: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bhavna Agrawal, Peter Feldmann, Sani R. Nassif, Tomasz J. Nowicki, Grzegorz Michal Swirszcz
  • Publication number: 20070225958
    Abstract: A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
    Type: Application
    Filed: February 16, 2006
    Publication date: September 27, 2007
    Applicant: International Business Machines Corporation
    Inventors: Emrah Acar, Bhavna Agrawal, Peter Feldmann, Ying Liu, Steven Walker
  • Publication number: 20060277511
    Abstract: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 7, 2006
    Inventors: Bhavna Agrawal, Peter Feldmann, Sani Nassif, Tomasz Nowicki, Grzegorz Swirszcz