Patents by Inventor Bhavya LOKASANI

Bhavya LOKASANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND APPARATUS TO REDUCE TIME TO PROGRAM SINGLE LEVEL CELL BLOCKS IN A NON-VOLATILE MEMORY
    Publication number: 20240013839
    Abstract: NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Inventors: Sagar UPADHYAY, Aliasgar S. MADRASWALA, Bhavya LOKASANI, Pratyush CHANDRAPATI, Tarek Ahmed AMEEN BESHARI