Patents by Inventor Bhawana Singh Nirwan

Bhawana Singh Nirwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power supply glitch detector
    Patent number: 10156595
    Abstract: A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vglitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vtrip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage Vbias, wherein Vbias is chosen such that either both conditions (Vbias<Vtrip) and (Vbias+Vglitch>Vtrip) or both conditions (Vbias>Vtrip) and (Vbias?Vglitch<Vtrip) are always true.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 18, 2018
    Assignee: MICROSEMI SOC CORP.
    Inventors: Bhawana Singh Nirwan, Abhishek Lal
  • Power Supply Glitch Detector
    Publication number: 20180164351
    Abstract: A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vglitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vtrip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage Vbias, wherein Vbias is chosen such that either both conditions (Vbias<Vtrip) and (Vbias+Vglitch>Vtrip) or both conditions (Vbias>Vtrip) and (Vbias?Vglitch<Vtrip) are always true.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 14, 2018
    Inventors: Bhawana Singh Nirwan, Abhishek Lal