Abstract: An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of less than a word in length, the write data stored within a FIFO memory device 18 associated with a first bus agent reflects the result of a read/modify/write type of access wherein a byte or half word has been merged by a local processor 12 with a cache word. Memory control lines driven to a system bus 20 indicate to a memory controller 22 that a write operation is to be accomplished as a word write, thereby eliminating the additional time required to achieve a read/modify/write memory controller cycle. To prevent the occurrence of a problem wherein another bus agent, such as another CPU or an I/O device, writes to a system memory 24 during an interval of time that the word of data is temporarily buffered within the FIFO there is provided circuitry for detecting an external write made to the system memory.