Patents by Inventor Bhimantoro Y Prasetyo

Bhimantoro Y Prasetyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6891362
    Abstract: An input signal is a complex vector whose phase is a coherent measurement of the phase rotation occurring between two separated symbols of a received CDMA signal. A processing block (30) provides a first signal showing the magnitude and the sign of the imaginary part of the input signal, and a second signal showing the magnitude and sign of the real part of the input signal to an initialisation block (31). A quadrant determination block (32) examines the signs of the signals to determine the quadrant in which the phase of the input signal exists. A comparator block (33) determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block (35) to form a multiplied signal, and a counter incremented, initially from zero. The comparator block (33) then determines if the multiplied signal is greater than or equal to the magnitude of the second signal.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: May 10, 2005
    Assignee: Analog Devices B.V.
    Inventors: Diego Giancola, Bhimantoro Y Prasetyo
  • Publication number: 20040032245
    Abstract: An input signal is a complex vector whose phase is a coherent measurement of the phase rotation occurring between two separated symbols of a received CDMA signal. A processing block (30) provides a first signal showing the magnitude and the sign of the imaginary part of the input signal, and a second signal showing the magnitude and sign of the real part of the input signal to an initialisation block (31). A quadrant determination block (32) examines the signs of the signals to determine the quadrant in which the phase of the input signal exists. A comparator block (33) determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block (35) to form a multiplied signal, and a counter incremented, initially from zero. The comparator block (33) then determines if the multiplied signal is greater than or equal to the magnitude of the second signal.
    Type: Application
    Filed: May 21, 2003
    Publication date: February 19, 2004
    Inventors: Diego Giancola, Bhimantoro Y Prasetyo