Patents by Inventor Bhramar Vatsa

Bhramar Vatsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070169059
    Abstract: This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.
    Type: Application
    Filed: July 7, 2006
    Publication date: July 19, 2007
    Applicant: Poseidon Design Systems Inc.
    Inventors: Soorgoli Halambi, Sarang Shelke, Bhramar Vatsa, Dibyapran Sanyal, Nishant Nakate, Ramanujan Valmiki, Sai Atmakuru, William Salefski, Vidya Praveen