Abstract: An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal.

Abstract: An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal.

Abstract: A circuit and corresponding method for a precision floating gate voltage reference that uses a feedback loop, conduction of tunnel devices, and a bandgap cell to accurately program a desired charge level on a floating gate and provide a predictable and programmable temperature coefficient parameter for such voltage reference. In one embodiment, a bandgap cell is coupled through a capacitor to the floating gate storage node for providing a voltage source for canceling the temperature coefficient (TC) of the storage capacitor. The circuit and method enables TC to be minimized by either choosing the proper voltage source characteristics or alternatively, by choosing the proper ratio of two capacitors. The bandgap cell can alternatively be designed to have positive TC (PTAT voltage sources) or negative TC (VBE junction).

Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Abstract: An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors.

Abstract: A selectable reference voltage circuit for a digital-to-analog converter (DAC) which includes an input terminal for receiving an external reference voltage, a voltage comparator having two inputs and an output, one input for receiving the reference voltage and the other for receiving a predetermined voltage, the comparator providing one of two possible output voltages based upon the relationship of the magnitudes of the reference voltage and the predetermined voltage. The circuit includes a multiplexer having a control input coupled to receive as an input signal the output of the comparator, and having two inputs for receiving input voltage signals, one for receiving the voltage on the reference voltage input terminal and the other for receiving an on-chip generated reference voltage, the multiplexer selecting as an output voltage one of the two input voltages determined by the input signal at its control input.

Abstract: An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks.

Abstract: A clock signal distribution network in a microprocessor of a computer system for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal.

Abstract: A clock signal distribution network in a microprocessor for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal.

Abstract: In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.

Abstract: An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal.