Patents by Inventor Bhushan Borole
Bhushan Borole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082161Abstract: A lyophilized pharmaceutical composition of hydrolytically unstable pharmaceutical compounds, such as phenobarbital or salts thereof, is provided. An aqueous solution for injection of phenobarbital or salts thereof that is reconstituted from the lyophilized pharmaceutical composition is provided. The pharmaceutical compositions of the present disclosure have an ethanol content in the range from about 5000 ppm to about 70000 ppm. The composition of the present disclosure, in certain embodiments, is stable following two years of storage, wherein the total impurities do not exceed 0.5%. The pharmaceutical compositions of the present disclosure may be used for the treatment of neonatal seizures.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: SUN PHARMA ADVANCED RESEARCH COMPANY LIMITEDInventors: Malay SHAH, Bhushan BOROLE, Ravi PATEL, Ajay Jaysingh KHOPADE
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Patent number: 11874715Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: GrantFiled: October 14, 2022Date of Patent: January 16, 2024Assignee: INTEL CORPORATIONInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 11857683Abstract: The present invention relates to a lyophilized pharmaceutical composition of hydrolytically unstable pharmaceutical compounds, such as phenobarbital or salts thereof. The present invention also relates to an aqueous solution for injection of phenobarbital or salts thereof that is reconstituted from the lyophilized pharmaceutical composition. The pharmaceutical compositions of the present disclosure have an ethanol content in the range from about 5000 ppm to about 70000 ppm. The composition of the present disclosure, in certain embodiments, is stable following two years of storage, wherein the total impurities do not exceed 0.5%. The pharmaceutical compositions of the present disclosure may be used for the treatment of neonatal seizures.Type: GrantFiled: April 7, 2022Date of Patent: January 2, 2024Assignee: SUN PHARMA ADVANCED RESEARCH COMPANY LIMITEDInventors: Malay Shah, Bhushan Borole, Ravi Patel, Ajay Jaysingh Khopade
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Publication number: 20230031957Abstract: The present invention relates to a lyophilized pharmaceutical composition of hydrolytically unstable pharmaceutical compounds, such as phenobarbital or salts thereof. The present invention also relates to an aqueous solution for injection of phenobarbital or salts thereof that is reconstituted from the lyophilized pharmaceutical composition. The pharmaceutical compositions of the present disclosure have an ethanol content in the range from about 5000 ppm to about 70000 ppm. The composition of the present disclosure, in certain embodiments, is stable following two years of storage, wherein the total impurities do not exceed 0.5%. The pharmaceutical compositions of the present disclosure may be used for the treatment of neonatal seizures.Type: ApplicationFiled: April 7, 2022Publication date: February 2, 2023Applicant: SUN PHARMA ADVANCED RESEARCH COMPANY LIMITEDInventors: Malay SHAH, Bhushan BOROLE, Ravi PATEL, Ajay Jaysingh KHOPADE
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Publication number: 20230030396Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: ApplicationFiled: October 14, 2022Publication date: February 2, 2023Applicant: Intel CorporationInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 11493974Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: GrantFiled: August 14, 2020Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 10983581Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 31, 2017Date of Patent: April 20, 2021Assignee: Intel CorporationInventors: Sanjeev Jahagirdar, Altug Koker, Yoav Harel, Kenneth Brand, Chandra Gurram, Eric Finley, Bhushan Borole, Carlos Nava Rodriguez
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Publication number: 20210064111Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: ApplicationFiled: August 14, 2020Publication date: March 4, 2021Applicant: Intel CorporationInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 10747286Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: GrantFiled: June 11, 2018Date of Patent: August 18, 2020Assignee: INTEL CORPORATIONInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Publication number: 20190377395Abstract: Embodiments are generally directed to dynamic power budget allocation in a multi-processor system. An embodiment of an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: ApplicationFiled: June 11, 2018Publication date: December 12, 2019Applicant: Intel CorporationInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 10410699Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.Type: GrantFiled: June 29, 2018Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Anupama A. Thaploo, Bhushan Borole, Muhammad M. Khellah, Pascal A. Meinerzhagen
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Publication number: 20190204894Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 31, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Sanjeev Jahagirdar, Altug Koker, Yoav Harel, Kenneth Brand, Chandra Gurram, Eric Finley, Bhushan Borole, Carlos Nava Rodriguez
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Patent number: 10062429Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.Type: GrantFiled: April 17, 2017Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: Bhushan Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu