Patents by Inventor Bhushan M. Borole

Bhushan M. Borole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11175719
    Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Bhushan M. Borole, Wenyin Fu, Kamal Sinha, Joydeep Ray
  • Patent number: 11176990
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhishek R. Appu
  • Patent number: 11169850
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu, Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Eric J. Asperheim, Guei-Yuan Lueh, David Puffer, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Josh B. Mastronarde, Linda L. Hurd, Travis T. Schluessler, Tomasz Janczak, Abhishek Venkatesh, Kai Xiao, Slawomir Grajewski
  • Publication number: 20210294560
    Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: January 29, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Altug Koker, Michael Apodaca, Kai Xiao, Jeffery S. Boles, Adam T. Lake, David M. Cimini, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Philip R. Laws, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Wenyin Fu, Nikos Kaburlasos, Prasoonkumar Surti, Bhushan M. Borole
  • Patent number: 11106264
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Patent number: 11080810
    Abstract: By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Wenyin Fu, Abhishek R. Appu, Bhushan M. Borole, Altug Koker, Nikos Kaburlasos, Kamal Sinha
  • Publication number: 20210109589
    Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 30, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Deepak S. Vembar, Abhishek R. Appu, Ankur N. Shah
  • Publication number: 20210065779
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 4, 2021
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhishek R. Appu
  • Publication number: 20210035257
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 4, 2021
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Patent number: 10908865
    Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hughes Labbe, Altug Koker, Michael Apodaca, Kai Xiao, Jeffery S. Boles, Adam T. Lake, David M. Cimini, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Philip R. Laws, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Wenyin Fu, Nikos Kaburlasos, Prasoonkumar Surti, Bhushan M. Borole
  • Patent number: 10901909
    Abstract: In accordance with some embodiments, a separate pipe is used in graphics processor for handling accesses, namely reads, to read only (RO) surfaces within caches. Moreover, the caches may have defined read only section and defined read write (RW) sections. The read only section may be accessed through a dedicated read only pipe and the read write section may be accessed through a read write pipe for those surfaces that can also be written. Thus, the read only sections are handled in a read only fashion without the need to accommodate writes.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Kamal Sinha, Prasoonkumar Surti, Wenyin Fu, Bhushan M. Borole, Vasanth Ranganathan
  • Publication number: 20200349091
    Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 5, 2020
    Inventors: Abhishek R. Appu, Joydeep Ray, James A. Valerio, Altug Koker, Prasoonkumar Surti, Balaji Vembu, Wenyin Fu, Bhushan M. Borole, Kamal Sinha
  • Patent number: 10817012
    Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Iqbal R. Rajwani, Altug Koker, Bhushan M. Borole, Kamal Sinha, Abhishek R. Appu, Anupama A. Thaploo, Sunil Nekkanti, Wenyin Fu
  • Patent number: 10790010
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu
  • Patent number: 10761591
    Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Deepak S. Vembar, Abhishek R. Appu, Ankur N. Shah
  • Patent number: 10762877
    Abstract: In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Jaydeep P. Kulkarni, Bhushan M. Borole, Abhishek R. Appu, Altug Koker, Kamal Sinha, Wenyin Fu
  • Publication number: 20200272215
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 28, 2020
    Publication date: August 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Patent number: 10754809
    Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Iqbal R. Rajwani, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
  • Patent number: 10748238
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Publication number: 20200210238
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu, Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Eric J. Asperheim, Guei-Yuan Lueh, David Puffer, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Josh B. Mastronarde, Linda L. Hurd, Travis T. Schluessler, Tomasz Janczak, Abhishek Venkatesh, Kai Xiao, Slawomir Grajewski