Patents by Inventor Bhushan Shanti Asuri
Bhushan Shanti Asuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210099140Abstract: An amplifier circuit includes an amplifier, a balun comprising a primary side having a primary inductance and a secondary side having a secondary inductance, the primary side coupled to an output of the amplifier, the secondary side coupled to a first output path of the amplifier circuit and a second output path of the amplifier circuit, a shunt inductance coupled to the first output path; and a compensating inductance in the balun, the compensating inductance coupled between a first node and a second node, the first node coupling the compensating inductance to the first output path, the second node coupling the secondary inductance to the compensating inductance.Type: ApplicationFiled: October 1, 2019Publication date: April 1, 2021Inventors: Muhammad HASSAN, Bhushan Shanti ASURI, Mahim RANJAN
-
Publication number: 20210099197Abstract: An apparatus is disclosed for transceiving signals in multiple modes. In example implementations, an apparatus includes a transceiver that includes a first amplifier; a mixer having at least one input node and at least one output node, with the at least one input node coupled to the first amplifier; and a second amplifier coupled to the at least one output node of the mixer. The transceiver also includes a first register coupled to the first amplifier and a second register coupled to the second amplifier. The transceiver further includes at least one memory realizing a lookup table. The at least one memory is coupled to the first register and the second register. The lookup table includes a first portion corresponding to a first mode of the transceiver and a second portion corresponding to a second mode of the transceiver.Type: ApplicationFiled: September 30, 2020Publication date: April 1, 2021Inventors: Chuan Wang, Li Liu, Kevin Hsi-Huai Wang, Bhushan Shanti Asuri, Kang Yang, Shrenik Patel
-
Publication number: 20210091819Abstract: Wireless communication system may be configured to use different frequency bands for uplink communication and downlink communication. For example, a wireless system may use multiple frequency bands for downlink with carrier aggregation, and the wireless system may use only one frequency band for uplink. Up-conversion and down-conversion between baseband signals and RF signals, using a fixed frequency local oscillator signal may cause energy leak to an adjacent frequency band during transmission of signal and may result in interferences to other radio communication devices using the adjacent bands. To limit the amount of energy that leaks out of its assigned radio frequency bands, the UE may use local oscillator signals with different frequencies for up-conversion and down-conversion and may switch the frequencies of the local oscillator signals between reception of downlink signals and transmission of uplink signals.Type: ApplicationFiled: September 20, 2019Publication date: March 25, 2021Inventors: Bhushan Shanti Asuri, Yiwu Tang, Shrenik Patel
-
Patent number: 10686476Abstract: An RF-DAC transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.Type: GrantFiled: May 20, 2019Date of Patent: June 16, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Nitz Saputra, Chen Jiang, Behnam Sedighi, Ibrahim Ramez Chamas, Bhushan Shanti Asuri, Dongwon Seo
-
Publication number: 20200169266Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Inventors: Shahin MEHDIZAD TALEIE, Behnam SEDIGHI, Dongwon SEO, Parisa MAHMOUDIDARYAN, Bhushan Shanti ASURI, Sang-June PARK, Shrenik PATEL
-
Patent number: 10666285Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: GrantFiled: November 28, 2018Date of Patent: May 26, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Behnam Sedighi, Dongwon Seo, Parisa Mahmoudidaryan, Bhushan Shanti Asuri, Sang-June Park, Shrenik Patel
-
Patent number: 10630239Abstract: In certain aspects, an apparatus includes a plurality of phase generators configured to generate a first plurality of local oscillator (LO) phase signals, wherein the plurality of phase generators includes a first set of phase generators and a second set of phase generators. The apparatus also includes a duty cycle generator coupled to the plurality of phase generators, wherein the duty cycle generator is configured to receive the first plurality of LO phase signals and to generate a second plurality of LO phase signals by converting a duty cycle of each of the first plurality of LO phase signals. The first set of phase generators is located adjacent to a first side of the duty cycle generator and the second set of phase generators is located adjacent to a second side of the duty cycle generator, the second side being opposite the first side.Type: GrantFiled: June 12, 2019Date of Patent: April 21, 2020Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Gajanan Maroti Devpuje, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
-
Patent number: 10608598Abstract: In an example aspect, an apparatus includes a balanced power amplifier, which performs amplification in the presence of a variable antenna impedance. The balanced power amplifier includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.Type: GrantFiled: June 28, 2018Date of Patent: March 31, 2020Assignee: QUALCOMM Technologies, Inc.Inventors: Chuan Wang, Li Liu, Kevin Hsi Huai Wang, Bhushan Shanti Asuri, Gurkanwal Sahota, Francesco Carrara
-
Patent number: 10575279Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.Type: GrantFiled: April 1, 2016Date of Patent: February 25, 2020Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Jingcheng Zhuang, Praveen Sampath, Shrenik Patel, Jeremy Darren Dunworth, Lai Kan Leung, Gurkanwal Singh Sahota, Jong Min Park
-
Publication number: 20200007092Abstract: An apparatus is disclosed for amplification in presence of a variable antenna impedance. In an example aspect, the apparatus comprises a balanced power amplifier, which includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Chuan Wang, Li Liu, Kevin Hsi Huai Wang, Bhushan Shanti Asuri, Gurkanwal Sahota, Francesco Carrara
-
Patent number: 10498298Abstract: An apparatus is disclosed for time-division duplex dynamic transceiver isolation. In an example aspect, the apparatus includes an antenna, a power amplifier circuit including at least one power-amplifying path, a low-noise amplifier, and a time-division duplex interface circuit. The interface includes at least one transmit node coupled to the at least one power-amplifying path, a receive node coupled to the low-noise amplifier, and an antenna node. The antenna node is coupled to the at least one transmit node, the receive node, and the antenna. The interface circuit is configured to connect the at least one transmit node, the receive node, and the antenna node together at both a first time and a second time. The interface circuit is configured to isolate the receive node from the antenna node at the first time and isolate the at least one transmit node from the antenna node at the second time.Type: GrantFiled: August 10, 2018Date of Patent: December 3, 2019Assignee: QUALCOMM IncorporatedInventors: Chuan Wang, Li Liu, Bhushan Shanti Asuri, Kevin Hsi Huai Wang, Yunfei Feng
-
Patent number: 10454509Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: GrantFiled: April 25, 2018Date of Patent: October 22, 2019Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Ashok Swaminathan, Shahin Mehdizad Taleie, Yen-Wei Chang, Vinod Panikkath, Sameer Vasantlal Vora, Ayush Mittal, Tonmoy Biswas, Sy-Chyuan Hwu, Zhilong Tang, Ibrahim Chamas, Ping Wing Lai, Behnam Sedighi, Dongwon Seo, Nitz Saputra
-
Patent number: 10447280Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.Type: GrantFiled: September 21, 2017Date of Patent: October 15, 2019Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Gajanan Maroti Devpuje, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan
-
Publication number: 20190288722Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: ApplicationFiled: April 25, 2018Publication date: September 19, 2019Inventors: Bhushan Shanti ASURI, Krishnaswamy THIAGARAJAN, Ashok SWAMINATHAN, Shahin MEHDIZAD TALEIE, Yen-Wei CHANG, Vinod PANIKKATH, Sameer Vasantlal VORA, Ayush MITTAL, Tonmoy BISWAS, Sy-Chyuan HWU, Zhilong TANG, Ibrahim CHAMAS, Ping Wing LAI, Behnam SEDIGHI, Dongwon SEO, Nitz SAPUTRA
-
Patent number: 10348528Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.Type: GrantFiled: March 29, 2017Date of Patent: July 9, 2019Assignee: QUALCOMM IncorporationInventors: Ayush Mittal, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Sameer Vasantlal Vora, Mahim Ranjan
-
Patent number: 10348246Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.Type: GrantFiled: January 4, 2018Date of Patent: July 9, 2019Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri, Mahim Ranjan
-
Publication number: 20190207558Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.Type: ApplicationFiled: January 4, 2018Publication date: July 4, 2019Inventors: Ayush MITTAL, Krishnaswamy THIAGARAJAN, Bhushan Shanti ASURI, Mahim RANJAN
-
Patent number: 10305522Abstract: A communication circuit may include mixers configured to generate voltage mode outputs. The communication circuit may further include voltage nodes configured to sum the voltage mode outputs produced by the mixers to generate intermediate voltage mode signals. The communication circuit may further include transconductors configured to convert the intermediate voltage mode signals to intermediate current mode signals. The communication circuit may further include at least one current node configured to sum the intermediate current mode signals to generate at least one mixer output signal.Type: GrantFiled: April 25, 2018Date of Patent: May 28, 2019Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Krishnaswamy Thiagarajan
-
Publication number: 20190089358Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Ayush Mittal, Gajanan Maroti Devpuje, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan
-
Publication number: 20180139078Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.Type: ApplicationFiled: March 29, 2017Publication date: May 17, 2018Inventors: Ayush Mittal, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Sameer Vasantlal Vora, Mahim Ranjan