Patents by Inventor Bhushan TALELE

Bhushan TALELE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ramp generator for multilevel class-D amplifiers
    Patent number: 10965279
    Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yogesh Kumar Ramadass, Bhushan Talele, Shailendra Kumar Baranwal, Yinglai Xia, Junmin Jiang
  • RAMP GENERATOR FOR MULTILEVEL CLASS-D AMPLIFIERS
    Publication number: 20200304111
    Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 24, 2020
    Inventors: Yogesh Kumar RAMADASS, Bhushan TALELE, Shailendra Kumar BARANWAL, Yinglai XIA, Junmin JIANG