Abstract: A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Abstract: A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold.

Abstract: A printed circuit board includes a circuit trace and a connector pad. The connector pad provides electrical and mechanical mounting of a connector lead of a surface mount device and provides a circuit path between the surface mount device and the circuit trace. The connector pad includes 1) a connector pad base electrically coupled to the circuit trace, and 2) a first connector pad island electrically isolated from the connector pad base. The connector pad base has a length that is substantially equal to a length of a contact portion of the connector lead.

Abstract: A circuit board pad mounting orientation system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. At least one connector pad receives the signal transmission line adjacent a first end of that connector pad. At least one connector pad includes a second end that provides a reduction in a width of that connector pad to indicate a mounting orientation for coupling to the connector pad that receives the signal transmission line. In a specific example, a first connector pad receives the signal transmission line, includes the first end, and includes the second end that is opposite the first connector pad from the first end and that provides the reduction in the width of the first connector pad to indicate the mounting orientation for coupling to the first connector pad.

Abstract: In accordance with some embodiments of the present disclosure, a connector may include a housing and a pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of a device comprising the connector. A body of the pin is formed of a material having a first conductivity. The pin may include a first portion between a proximal point of the pin and a medial point of the pin, and a second portion between the medial point of the pin and a distal point of the pin. The medial point of the pin is proximate to a point of electrical contact of the pin with another pin. The second portion is at least partially covered by a layer of material having a second conductivity that is lower than the first conductivity.

Abstract: An Information handling system (IHS) includes a circuit board assembly with surface mount technology (SMT) pad structure. Landing pad(s) attached to circuit board substrate have a mounting area that receive an SMT connector pin onto adjacent pair of differential contact strips plated to nonconductive surface and extending longitudinally in parallel alignment. A return current strip is longitudinally aligned, adjacent to the differential contact strips on a first lateral side. The return current strip is connected to a ground plane of the circuit board substrate. Converging narrowing of the adjacent differential contact strip increases separation from a distal end of the return current strip. The separation improves signal integrity by reducing fringe effects, increasing impedance, and quenching resonance. A surface mount device (SMD) has one or more connector pins that are attached to the one or more landing pads to conduct the high-speed communication signal.

Abstract: A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.

Abstract: A differential pair contact resistance asymmetry compensation system includes a board with a differential trace pair. A receiver device is coupled to the differential trace pair via a receiver device connector interface, and a transmitter device is coupled to the differential trace pair via a transmitter device connector interface. The transmitter device transmits a contact resistance compensation data stream to the receiver device via the differential trace pair. The transmitter device then adjusts an impedance provided by the transmitter device to compensate for a contact resistance asymmetry in the transmitter device connector interface. When the transmitter device determines that differential trace pair signal transmission capabilities for the differential trace pair in transmitting the contact resistance compensation data stream have improved in response to the adjustment of the impedance provided by the transmitter device, it sets the impedance provided by the transmitter device.

Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.

Abstract: An electrical connector element, for use on a printed circuit board assembly, includes a soldering pad having a longitudinal length and a cross-sectional width. The soldering pad is configured to be electrically-coupleable to a PCB device conductor. At least one impedance inducing feature is positioned along the longitudinal length of the soldering pad.

Abstract: A cable includes first and second electrically conducting wires, each of the two wires surrounded by a respective isolating dielectric material for a length of the respective wire. A signal propagation skew between the first and second wires may be detected, and a dielectric constant associated with a wire may be changed to mitigate the detected signal propagation skew. The dielectric constant may be changed by removing or adding dielectric material from or to the wire.

Abstract: A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

Abstract: A cable assembly includes a printed circuit board having a first surface and a second surface. A first post and a second post extend from one side of the printed circuit board. A first signal pad, a second signal pad, and a first ground pad are each coupled to the first surface. A first cable has a first signal wire at least partially covered by a first insulator and a second signal wire at least partially covered by a second insulator. The first cable further has a first ground shield at least partially covering the first and second insulators. A first end of a first cable is mounted between the first and second posts. A conductive attachment couples the first ground shield to the first ground pad.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

Abstract: An information handling system communicates information across a physical link with high and low signal values sent at a unit interval. Feed forward equalization improves signal transfer with pre-emphasis of low-to-high signals and de-emphasis of high-to-low signals lasting for a fraction of the unit interval, such as one-half or one-quarter of the unit interval. Fractional unit interval pre-emphasis and de-emphasis reduce inter symbol interference to improve frequency domain eye structure at the physical link receiver.

Abstract: A circuit board assembly of an information handling system has stepped diameter vias that carry communication signals through printed circuit board (PCB) substrates. Each stepped diameter via has a first barrel portion of a first diameter that is drilled through a first portion of the PCB substrates and that is at least lined with a conductive material to electrically conduct a selected one of: (i) a direct current and (ii) a communication signal from an outer layer to an internal layer of the more than one PCB substrate. Each stepped diameter via further includes a second barrel portion that extends from the first barrel portion deeper into the PCB substrates. The second barrel portion has a second diameter that is less than the first diameter and the smaller second diameter improves signal integrity (SI).

Abstract: A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver.

Abstract: A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design and multiplying an input spectrum with each of the transfer functions to provide a plurality of results. The method further includes summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal.

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.