Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: An exemplary method includes receiving a hybrid fin device layout for a hybrid fin device that includes a gate disposed over a single-fin active region and a multi-fin active region. The single-fin active region and the multi-fin active region extend lengthwise along a first direction. The gate extends lengthwise along a second direction, the second direction is different than the first direction, and the gate has a width along the first direction. The single-fin active region and a first portion of the gate form a first fin-based device having a first electrical characteristic. The multi-fin active region and a second portion of the gate form a second fin-based device having a second electrical characteristic that is different than the first electrical characteristic. The method further includes tuning the width of the gate to reduce a difference between the first electrical characteristic and the second electrical characteristic.

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.