Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: Systems and methods for designing a dummy pattern layout for improving surface flatness of a wafer are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: Systems and methods for designing a dummy pattern layout for improving surface flatness of a wafer are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: A housing includes a plastic panel and a metal insert. The plastic panel includes an outer surface and an inner surface, the plastic panel defines a through groove through the outer surface and the inner surface. The metal insert is integrally molded to the inner surface of the plastic panel covering, the through groove so it is capable of seeing a metallic pattern corresponding to the through groove viewing through the through groove.

Abstract: A button assembly for an electronic device includes a housing and a button. The housing defines an opening having two latching blocks. The button is received in the opening. The button includes a button body, two opposite engaging blocks, and two arcuate arms. The engaging blocks are formed on opposite sides of one end of the button body, the arcuate arms are formed on opposite sides of another end of the button body. Each arcuate arm forms an archimedean spiral.

Abstract: A housing includes a plastic panel and a metal insert. The he plastic panel includes an outer surface and an inner surface, the plastic panel defines a through groove through the outer surface and the inner surface. The metal insert is integrally molded to the inner surface of the plastic panel covering the through groove so it is capable of seeing a metallic pattern corresponding to the through groove viewing through the through groove.

Abstract: A button assembly for an electronic device includes a housing and a button. The housing defines an opening having two latching blocks. The button is received in the opening. The button includes a button body, two opposite engaging blocks, and two arcuate arms. The engaging blocks are formed on opposite sides of one end of the button body, the arcuate arms are formed on opposite sides of another end of the button body. Each arcuate arm forms an archimedean spiral.