Patents by Inventor Bi-Shen LEE

Bi-Shen LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220406916
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11527717
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Tzu-Chung Tsai, Fa-Shen Jiang, Bi-Shen Lee
  • Patent number: 11527713
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20220393101
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Application
    Filed: July 29, 2021
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220392906
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Publication number: 20220367810
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 17, 2022
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Tzu-Chung Tsai, Fa-Shen Jiang, Bi-Shen Lee
  • Publication number: 20220367493
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 17, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220359823
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20220336739
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Publication number: 20220336737
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Publication number: 20220320123
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Bi-Shen Lee, Hsing-Lien Lin, Hsun-Chung Kuang, Yi Yang Wei
  • Publication number: 20220310635
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 29, 2022
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220285374
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 8, 2022
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Publication number: 20220278115
    Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
    Type: Application
    Filed: July 26, 2021
    Publication date: September 1, 2022
    Inventors: Yi Yang Wei, Tzu-Yu Lin, Bi-Shen Lee, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11430951
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Patent number: 11404638
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 11393833
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer is arranged between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based upon one or more voltages applied to the bottom electrode or the top electrode. A seed layer is arranged between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic crystal phase.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hsing-Lien Lin, Hsun-Chung Kuang, Yi Yang Wei
  • Publication number: 20220052260
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Bi-Shen Lee
  • Publication number: 20220037589
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Publication number: 20220028874
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Application
    Filed: December 17, 2020
    Publication date: January 27, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh