Patents by Inventor Bi Yuan
Bi Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138272Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11706543Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.Type: GrantFiled: November 19, 2021Date of Patent: July 18, 2023Assignee: OmniVision Technologies, Inc.Inventors: Chengcheng Xu, Rui Wang, Bi Yuan, Liang Zuo
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Publication number: 20220078365Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Inventors: Chengcheng Xu, Rui Wang, Bi Yuan, Liang Zuo
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Patent number: 11218659Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.Type: GrantFiled: December 9, 2019Date of Patent: January 4, 2022Assignee: OMNIVISION TECHNOLOGIES, INC.Inventors: Chengcheng Xu, Rui Wang, Bi Yuan, Liang Zuo
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Publication number: 20210176417Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.Type: ApplicationFiled: December 9, 2019Publication date: June 10, 2021Inventors: Chengcheng Xu, Rui Wang, Bi Yuan, Liang Zuo
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Patent number: 9961281Abstract: An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.Type: GrantFiled: June 10, 2016Date of Patent: May 1, 2018Assignee: OmniVision Technologies, Inc.Inventors: Bi Yuan, Liping Deng, Yingkan Lin, Liang Zuo, Yuxin Wang
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Patent number: 9848140Abstract: A readout circuit for use in an image sensor includes a system ramp generator coupled to generate a system ramp signal. A plurality of analog-to-digital converters is coupled to a plurality of column bitlines from a pixel array to receive corresponding analog column image signals. An isolation ramp buffer is coupled between the system ramp generator and the analog-to-digital converters. The isolation ramp buffer includes a single input to receive the system ramp signal, and a plurality of isolated outputs. Each of the isolated outputs is coupled to provide an isolated column ramp signal to a corresponding analog-to-digital converter. Each of the of analog-to-digital converters is coupled to generate a corresponding digital column image signal in response to the corresponding analog column image signal and corresponding isolated column ramp signal.Type: GrantFiled: March 31, 2016Date of Patent: December 19, 2017Assignee: OmniVision Technologies, Inc.Inventors: Liping Deng, Min Qu, Bi Yuan, Yingkan Lin
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Publication number: 20170359532Abstract: An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.Type: ApplicationFiled: June 10, 2016Publication date: December 14, 2017Inventors: Bi Yuan, Liping Deng, Yingkan Lin, Liang Zuo, Yuxin Wang
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Publication number: 20170289470Abstract: A readout circuit for use in an image sensor includes a system ramp generator coupled to generate a system ramp signal. A plurality of analog-to-digital converters is coupled to a plurality of column bitlines from a pixel array to receive corresponding analog column image signals. An isolation ramp buffer is coupled between the system ramp generator and the analog-to-digital converters. The isolation ramp buffer includes a single input to receive the system ramp signal, and a plurality of isolated outputs. Each of the isolated outputs is coupled to provide an isolated column ramp signal to a corresponding analog-to-digital converter. Each of the of analog-to-digital converters is coupled to generate a corresponding digital column image signal in response to the corresponding analog column image signal and corresponding isolated column ramp signal.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Liping Deng, Min Qu, Bi Yuan, Yingkan Lin
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Patent number: 9571775Abstract: A ramp generator for use in readout circuitry includes an integrator coupled to receive a ramp generator input reference signal to generate a reference ramp signal coupled to be received by an analog to digital converter. A power supply compensation circuit that is coupled to generate the ramp generator input reference signal includes a delay circuit including a variable resistor and a filter capacitor coupled to receive a power supply signal. The variable resistor is tuned to match a delay ripple from the power supply to a bitline output. A capacitive voltage divider is coupled to the delay circuit to generate the ramp generator input reference signal. The capacitive voltage divider includes a first variable capacitor coupled to a second variable capacitor that are tuned to provide a capacitance ratio that matches a coupling ratio from the power supply to the bitline output.Type: GrantFiled: November 16, 2015Date of Patent: February 14, 2017Assignee: OmniVision Technologies, Inc.Inventors: Liang Zuo, Zhihao Xu, Bi Yuan, Liping Deng, Yuxin Wang
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Patent number: 9380208Abstract: A ramp generator includes a supply voltage sampling circuit coupled to sample a black signal supply voltage during a black signal readout, and an image signal supply voltage of the pixel cell during an image signal readout of a pixel cell. A first integrator circuit receives a buffered reference voltage, and an output of the supply voltage sampling circuit. First and second switches are coupled between the first integrator circuit and a first capacitor to transfer a signal representative of a difference between the image signal supply voltage and the black signal supply voltage to the first capacitor. A second integrator circuit is coupled to the first capacitor to generate an output ramp signal coupled to be received by an analog to digital converter. A starting value of the output ramp signal is adjusted in response to the difference between the image signal and the black signal supply voltage.Type: GrantFiled: April 13, 2015Date of Patent: June 28, 2016Assignee: OmniVision Technologies, Inc.Inventors: Bi Yuan, Quifeng Jin, Liping Deng, Liang Zuo
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Patent number: 8648913Abstract: A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC). The sub-ADC includes a comparator and a random offset controller. The comparator is coupled to compare a first analog signal received by the stage with a reference signal. The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC.Type: GrantFiled: April 15, 2011Date of Patent: February 11, 2014Assignee: OmniVision Technologies, Inc.Inventors: Liping Deng, Tie Jun Dai, Bi Yuan, Chien-Chen Chen
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Publication number: 20120262614Abstract: A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC). The sub-ADC includes a comparator and a random offset controller. The comparator is coupled to compare a first analog signal received by the stage with a reference signal. The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC.Type: ApplicationFiled: April 15, 2011Publication date: October 18, 2012Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Liping Deng, Tie Jun Dai, Bi Yuan, Chien-Chen Chen