Abstract: An alginate hydrogel-based thin-film heat flux sensor for billet crystallizer includes an alginate hydrogel substrate. The alginate hydrogel substrate is configured in a U-shaped planar structure. The U-shaped planar structure includes a first side and a second side, and the first side is longer than the second side. An inner surface of the alginate hydrogel substrate is provided with a first film thermocouple and a second film thermocouple. The first film thermocouple is in crosslinking connection with the second film thermocouple.

Abstract: Briefly, embodiments of methods or systems for testing software modules are disclosed.

Abstract: Briefly, embodiments of methods or systems for testing software modules are disclosed.

Abstract: This invention provides a circuit and a method for very high-speed multiplexers. It provides a circuit that can produce an arbitrary number of multiple signal multiplexers. It also provides a circuit and a method which converts a parallel data bus into a serial data path. This invention contains an overlapped data generator, which takes in a data bus and outputs even and odd signals to a selective mux. It also contains a selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one serial data bit. It also contains a phase locked loop/delay locked loop, PLL/DLL, which receives a set of phase clocks and which outputs five evenly-phase-distributed clock signals to a data select signal generator. Finally, the circuit includes a data select signal generator, which receives said five evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus.

Abstract: This invention provides a circuit and a method for very high-speed multiplexers. It provides a circuit that can produce an arbitrary number of multiple signal multiplexers. It also provides a circuit and a method which converts a parallel data bus into a serial data path. This invention contains an overlapped data generator, which takes in a data bus and outputs even and odd signals to a selective mux. It also contains a selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one serial data bit. It also contains a phase locked loop/delay locked loop, PLL/UDLL, which receives a set of phase clocks and which outputs five evenly-phase-distributed clock signals to a data select signal generator. Finally, the circuit includes a data select signal generator, which receives said five evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus.