Patents by Inventor Biancun Xie

Biancun Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107665
    Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Biancun Xie, Shree Krishna Pandey, Chin-Kwan Kim, Ryan Lane, Charles David Paynter
  • Publication number: 20230402380
    Abstract: A package comprising a substrate, a bridge located in the substrate, a first integrated device coupled to the substrate and a second integrated device coupled to the substrate. The bridge includes a bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located in the at least one second bridge dielectric layer; and at least one bridge interconnect that extends through the at least one first bridge dielectric layer and the bridge substrate.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Biancun XIE, Shree Krishna PANDEY
  • Patent number: 11749661
    Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: September 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Biancun Xie, Shree Krishna Pandey
  • Patent number: 11626359
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: April 11, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Biancun Xie, Shree Krishna Pandey, Irfan Khan, Miguel Miranda Corbalan, Stanley Seungchul Song
  • Publication number: 20230005901
    Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Inventors: Biancun XIE, Shree Krishna PANDEY
  • Publication number: 20220344249
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 27, 2022
    Inventors: Biancun XIE, Shree Krishna PANDEY, Irfan KHAN, Miguel MIRANDA CORBALAN, Stanley Seungchul SONG
  • Publication number: 20200395300
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Biancun Xie, Jianyong Xie, Sujit Sharan, Debendra Mallik, Robert L. Sankman