Patents by Inventor Bianny BIAN

Bianny BIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • REDUCING INTERCONNECT TRAFFICS OF MULTI-PROCESSOR SYSTEM WITH EXTENDED MESI PROTOCOL
    Publication number: 20170242797
    Abstract: A processor includes a first core including a first cache including a cache line, a second core including a second cache, and a cache controller to set a flag stored in a flag section of the cache line of the first cache to one of a processor share (PS) state in response to data stored in the cache line being shared by the second cache, or to a global share (GS) state in response to the data stored in the first cache line being shared by a third cache of a second processor.
    Type: Application
    Filed: September 25, 2014
    Publication date: August 24, 2017
    Inventors: Kebing WANG, Bianny BIAN