Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.