Patents by Inventor Bibiche M. Geuskens
Bibiche M. Geuskens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10984855Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: GrantFiled: February 25, 2019Date of Patent: April 20, 2021Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
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Publication number: 20190362777Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: ApplicationFiled: February 25, 2019Publication date: November 28, 2019Applicant: Intel CorporationInventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
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Patent number: 10217509Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: GrantFiled: April 24, 2017Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammad M. Khellah
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Publication number: 20170243637Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: ApplicationFiled: April 24, 2017Publication date: August 24, 2017Inventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
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Patent number: 9633716Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: GrantFiled: January 6, 2016Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
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Patent number: 9627039Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.Type: GrantFiled: August 19, 2015Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Jaydeep P Kulkarni, Muhammad M Khellah, James W Tschanz, Bibiche M Geuskens, Vivek K De
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Publication number: 20160225438Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: ApplicationFiled: January 6, 2016Publication date: August 4, 2016Inventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
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Publication number: 20160141022Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.Type: ApplicationFiled: August 19, 2015Publication date: May 19, 2016Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De
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Patent number: 9299395Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: GrantFiled: March 26, 2012Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammad M. Khellah
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Patent number: 9153304Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.Type: GrantFiled: June 28, 2012Date of Patent: October 6, 2015Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De
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Publication number: 20150009751Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.Type: ApplicationFiled: March 26, 2012Publication date: January 8, 2015Inventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammad M. Khellah
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Patent number: 8868836Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.Type: GrantFiled: December 31, 2007Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Muhammad M. Khellah, Christopher Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, Gunjan H. Pandya
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Publication number: 20140003132Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Inventors: Jaydeep P. Kulkarni, Muhammad M Khellah, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De
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Patent number: 8467263Abstract: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.Type: GrantFiled: June 25, 2010Date of Patent: June 18, 2013Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De
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Patent number: 8094505Abstract: A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.Type: GrantFiled: October 9, 2009Date of Patent: January 10, 2012Assignee: Intel CorporationInventors: Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury
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Publication number: 20110317508Abstract: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Inventors: JAYDEEP P. KULKARNI, Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De
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Publication number: 20110085389Abstract: A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Inventors: Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury
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Publication number: 20090172283Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Muhammad M. Khellah, Christopher Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, Gunjan H. Pandya