Abstract: A extreme ultraviolet (EUV) mask blank having a reflective stack formed by depositing repeated periods of a silicon layer, a first barrier layer, a molybdenum layer, and a second barrier layer using atomic layer deposition is discussed. Precursors using silane and hydrogen are used to form the silicon layer. The first and second barrier layers are preferably different thicknesses of the same material and can be formed using precursors including diborane and methane. In one embodiment, the molybdenum layer is formed using precursors including hydrogen and molybdenum pentachloride or molybdenum pentaiodide. An EUV mask used to pattern a photoresist layer to form an integrated circuit is manufactured from the EUV mask blank.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.

Abstract: A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Abstract: A dielectric layer comprises lanthanum, aluminum, nitrogen, and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with among the lanthanum, nitrogen, or aluminum. An additional insulating layer may be formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Abstract: A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).

Abstract: The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.

Abstract: A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: A extreme ultraviolet (EUV) mask blank having a reflective stack formed by depositing repeated periods of a silicon layer, a first barrier layer, a molybdenum layer, and a second barrier layer using atomic layer deposition is discussed. Precursors using silane and hydrogen are used to form the silicon layer. The first and second barrier layers are preferably different thicknesses of the same material and can be formed using precursors including diborane and methane. In one embodiment, the molybdenum layer is formed using precursors including hydrogen and molybdenum pentachloride or molybdenum pentaiodide. An EUV mask used to pattern a photoresist layer to form an integrated circuit is manufactured from the EUV mask blank.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Abstract: The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.

Abstract: A vertical double gate semiconductor device (10) having separate, non-contiguous gate electrode regions (62, 64) is described. The separate gate electrode regions can be formed by depositing a gate electrode material (28) and anisotropically etching, planarizing or etching back the gate electrode material to form the separate gate electrode regions on either side of the vertical double gate semiconductor device. One (66) or two (68, 70) contacts are formed over the separate gate electrode regions that may or may not be electrically isolated from each other. If formed from polysilicon, the separate gate electrode regions are doped. In one embodiment, the separate gate electrode regions are doped the same conductivity. In another embodiment, an asymmetrical semiconductor device is formed by doping one separate gate electrode region n-type and the other separate gate electrode region p-type.

Abstract: The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Abstract: A dielectric layer comprises lanthanum, aluminum and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with respect to the lanthanum or aluminum. In another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Abstract: In accordance with a specific embodiment of the present invention, a method of forming a gate dielectric is disclosed. A semiconductor wafer is placed in a deposition chamber. The semiconductor wafer is heated and a precursor gas is flowed into the chamber. In one embodiment, the precursor comprises a moiety of silicon, oxygen, and a transition metal. In another embodiment, the moiety includes a group 2 metal.

Abstract: A method of forming a capacitor and transistor are disclosed. Initially, a substrate having a semiconductor material on a first surface is provided. A layer of strontium nitride is then deposited over the first surface and a gate electrode formed over the strontium nitride. Source and drains are then formed in the first surface disposed laterally adjacent to the gate electrode to leave a channel under the gate electrode. A dielectric layer may be formed over the layer of strontium nitride prior to forming the gate electrode. The dielectric layer may include strontium, titanium, and oxygen. In one embodiment, the dielectric layer and the layer of strontium nitride are epitaxial layers. In another embodiment the layer of strontium nitride is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). The dielectric layer may include strontium, oxygen, and nitrogen, such as strontium oxynitride formed by sputtering, CVD, or ALD.