Abstract: A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame.

Abstract: An integrated circuit package which utilizes a standard TAB tape that can couple a lead frame to one of a number of integrated circuit dies that have different outer dimensions. The TAB tape includes a sheet of polyimide which supports a plurality of conductive leads. The sheet has a rectangular center opening which provides clearance for the IC die. Adjacent to each edge of the center opening are a plurality of equally spaced contact openings which expose portions of the leads. The leads are coupled to the integrated circuit by attaching the contact portions to the surface pads of the die. The contact openings are located at various distances from the center opening so that the tape can accommodate different die sizes. The leads of the TAB tape are also attached to a lead frame through lead frame openings in the polyimide.

Abstract: A ceramic multilayer wiring substrate is provided on which the metallized wirings are partially altered to provide multiple resistivities without changing the other electrical properties associated with a particular physical wiring geometry. Sequentially positioning conductive materials of different resistivities along the length of each individual wiring produces a final wiring pattern where each individual wiring can have a different resistance from the other wirings. A multiple resistivity wiring pattern can maximize the operation of a semiconductor chip attached thereto, for example, by reducing the effect of electronic noise on the semiconductor.