Abstract: A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package.

Abstract: A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package.

Abstract: An apparatus for coupling an integrated circuit (IC) package to a printed circuit board. The apparatus includes an interposer an interposer having a plurality of connections suitable for surface mounting on corresponding pads of a printed circuit board (PCB). The plurality of connections is arranged in a grid array. The interposer further includes a plurality of plated through holes. The apparatus further includes a substrate having a plurality of pins. The substrate is coupled to the interposer by inserting each of the plurality of pins into a corresponding one of the plurality of plated through holes of the interposer. An IC package including an IC is mounted on the substrate.

Abstract: An apparatus for coupling an integrated circuit (IC) package to a printed circuit board. The apparatus includes an interposer an interposer having a plurality of connections suitable for surface mounting on corresponding pads of a printed circuit board (PCB). The plurality of connections is arranged in a grid array. The interposer further includes a plurality of plated through holes. The apparatus further includes a substrate having a plurality of pins. The substrate is coupled to the interposer by inserting each of the plurality of pins into a corresponding one of the plurality of plated through holes of the interposer. An IC package including an IC is mounted on the substrate.

Abstract: A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.

Abstract: An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.

Abstract: A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.

Abstract: An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.

Abstract: A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.

Abstract: A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.

Abstract: A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

Abstract: A capacitor having an aperture in a central portion of the capacitor is provided. Such a “windowframe” capacitor has capacitive material disposed within a housing of the capacitor in order to provide effective capacitance and reduced inductance. Further, a semiconductor package assembly having a semiconductor die and a windowframe capacitor is provided.

Abstract: Described are methods of manufacturing large substrate capacitors for multi-chip module applications and the like using procedures compatible with common semiconductor fabrication procedures. A capacitor is formed where the top electrode thereof is divided into a plurality of segmented pads which are initially electrically isolated from one another. Each segmented pad forms a capacitor with the underlying dielectric layer and bottom capacitor electrode. Each segmented capacitor is electrically tested, and defective ones are identified. A conductive layer is thereafter formed over the segmented pads such that the conductive layer is electrically isolated from the pads of defective capacitors. The conductive layer electrically couples the good capacitors in parallel to form a high-value bypass capacitor which has low parasitic inductance. Large embedded MCM bypass capacitors can thereby be fabricated with minimal impact to the overall manufacturing yield.

Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least on of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to the first direction.

Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least one of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to said first direction.