Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

Abstract: An architecture for transmitting both ATM cells and data packets via a single optical fiber and for receiving ATM cells and data packets via a single optical fiber. The architecture includes both a transmission convergence device (TCD) circuit and a segmentation-and-reassembly (SAR) circuit and is implemented as integrated circuits, preferably as part of a router to eliminate the need for a SONET multiplexer.

Abstract: An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

Abstract: A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.

Abstract: A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.

Abstract: An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

Abstract: A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.

Abstract: A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Control path circuitry includes a port calendar, a scheduler and an advanced multi-timing wheel shaper. The MS-SAR can be programmed such individual flows are shaped, or scheduled, or both.

Abstract: Improved methods and apparatus to facilitate switching Asynchronous Transfer Mode (ATM) cells through an ATM switching circuit are disclosed. The improved methods and apparatus facilitate the implementation of per virtual connection buffering, per virtual connection arbitration of ATM cells, and/or per virtual connection back-pressuring to improve switching efficiency and/or reduce the complexity and/or costs of the ATM switching circuit.

Abstract: An improved method and apparatus for automatically forming a virtual circuit in an ATM switch is disclosed. In one aspect of the invention, the virtual circuit may be used to transport an ATM data cell included in an associated communication session. The disclosed method includes the following operative steps. First, a configuration cell is created. Next the virtual circuit is formed by passing the configuration cell to a destination node by way of at least one connective node. The configuration cell updates and validates an associated connection table capable of defining a virtual link. The virtual link being part of the virtual circuit.

Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: Improved methods and apparatus to facilitate switching Asynchronous Transfer Mode (ATM) cells through an ATM switching circuit are disclosed. The improved methods and apparatus facilitate the implementation of per virtual connection buffering, per virtual connection arbitration of ATM cells, and/or per virtual connection back-pressuring to improve switching efficiency and/or reduce the complexity and/or costs of the ATM switching circuit.

Abstract: A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

Abstract: A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

Abstract: Apparatus and methods for retiming an STS-3 type signal are provided. The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs, and a byte which is synchronous with the TOH is tracked through the three FIFOs to provide an indication of the FIFO depth. A frame count is also kept to track the number of frames since a last pointer movement. Stuffs or destuffs are generated based on the FIFO depth as well as based on the frame count, with a stuff or destuff generated as quickly as four frames from a previous pointer movement if the FIFO is close to full or close to empty, and less quickly (e.g., at thirty-two frames from a previous pointer movement) if the FIFO is only starting to empty or to fill. Where the STS-3 type signal is a STS-3C signal, the decision on whether to stuff or destuff is made with reference to all three depth measurement circuits as all the STS-1 payloads must be stuffed or destuffed together.

Abstract: Methods and apparatus for quickly generating and transmitting SONET AIS signals are disclosed. Upon detecting a failure condition at the receiving side of a SONET terminating equipment, the SONET terminating equipment inserts an internal alarm control signal (e.g. a byte of all ones) into at least one predetermined transport overhead timeslot (e.g. E1). On the transmitting side, the transmitting SONET terminating equipment monitors the predetermined timeslot(s) and detects whether an indication of the internal alarm control signal has been received. If so, the transmitting SONET terminating equipment inserts an appropriate alarm in predetermined overhead and data timeslots of the outgoing SONET frame signal as specified by proposed AIS standards.

Abstract: Apparatus and methods for concatenating a plurality of lower level SONET signals into higher level SONET signals are provided. In generating a higher level SONET signal (e.g., STS-12C) using a plurality of lower level SONET signal processing apparatus (e.g., STS-3 type terminators), the J1 bytes of each lower level signal are tracked through the FIFOs of the apparatus to provide J1 byte control signals, and a logic circuit is provided having phase 3 of the outgoing STS-3 clock, and the J1 byte control signals from all the STS channels of the higher level signal as inputs. The J1 byte control signals from all the channels are combined as a J1ANDcomposite by utilizing a single bus which is coupled to each of the apparatus. The logic circuit inhibits a read of a J1 byte from any particular FIFO unless the J1ANDcomposite signal is high at phase 3 of the clock.